Abstract
Threshold voltage instabilities induced in p-channel power VDMOSFETs by pulsed negative bias temperature stressing are presented and compared with corresponding instabilities found after the static NBT stress. Degradation observed under the pulsed stress conditions depends on the frequency and duty cycle of stress voltage pulses, and is generally lower than the one found after the static NBT stress. Optimal frequency and duty cycle ranges for application of investigated devices are proposed as well. By selecting an appropriate combination of frequency range (1 kHz < f < 5 kHz) and duty cycle (about 25%), the pulsed stress-induced Δ V T can be reduced to a quarter of Δ V T found after the static NBT stress.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
