Pulsed Latches Research Articles

A simultaneous area, delay and leakage current reduction method for Linear Feedback Shift Register (LFSR) using pulsed latches and DTMOS transistors

In digital circuits, the shift registers are the significant elements having the ability of storing and transmitting the data in sequential manner.The linear feedback shift register (LFSR) uses large number of flips-flops that consumes maximum amount of power. To overcome this issue, this research work concentrates on the design of LFSR for the area efficient, power reduction, minimization of delay and leakage current. By replacing the d-flip-flop with the bi-enabled pulsed latch to reduce the power consumption and delay of the proposed LFSR design. For the minimization of area, leakage current and delay, the hybrid body bias generator with dynamic threshold MOS (BBG-DTMOS) is used. Moreover, the pulsed clock signal is generated in the digital circuit with the aid of hybrid BBG-DTMOS technique. The proposed LFSR design is implemented in the tanner EDA tool with the available CMOS model libraries. Based on the implementation result, the proposed LFSR area is 1824 μm2and its power consumption is 172μW at a 100 MHz clock frequency withVDD=5V. Furthermore, having the better performance in different corners of the method, reduces the propagation delay and leakage current in the digital circuit. The proposed LFSR design is compared with some of the shift registers such as unidirectional and bidirectional shift registers. The existing clock pulse generator such as conventional, delayed clock pulse, TIMBER logic, PTL-AND logic and multiplexer based clock pulse generator (MCPG) are compared with the proposed BBG-DTMOS technique.

Design of Multi-bit Pulsed Latches with Scan Input in CMOS ONK65 Technology

Design of Multi-bit Pulsed Latches with Scan Input in CMOS ONK65 Technology

Shift Register with Low Power and Area Efficient Pulsed Latches

Shift Register with Low Power and Area Efficient Pulsed Latches

Design of Low-Power ECG Sampling and Compression Circuit

Compressed Sensing (CS) has been applied to electrocardiogram monitoring in wireless sensor networks, but existing sampling and compression circuits consume too much hardware. This paper proposes a low-power and small-area sampling and compression circuit with an Analog-to-Digital Converter (ADC) and a CS module. The ADC adopts split capacitors to reduce hardware consumption and uses a calibration technique to decrease offset voltage. The CS module uses an approximate addition calculation for compression and stores the compressed data in pulsed latches. The proposed addition completes the accurate calculation of the high part and the approximate calculation of the low part. In a 55 nm CMOS process, the ADC has an area of 0.011 mm2 and a power consumption of 0.214 μW at 10 kHz. Compared with traditional design, the area and power consumption of the proposed CS module are reduced by 19.5% and 31.7%, respectively. The sampling and compression circuit area is 0.325 mm2, and the power consumption is 2.951 μW at 1.2 V and 100 kHz. The compressed data are reconstructed with a percentage root mean square difference of less than 2%. The results indicate that the proposed circuit has performance advantages of hardware consumption and reconstruction quality.

Self-Shut-Off Pulsed Latches for Minimizing Sequencing Overhead

In this study, a self-shut-off pulsed latch (SSPL) is proposed as sequencing elements for reducing the hold time constraint. As SSPL captures the data input after the clock edge, the large setup-time problem that exists in the master–slave flip-flop (MSFF) is eliminated. In addition, the transparency windows are closed immediately after successfully capturing the data input (self-shut-off), and the proposed SSPL is devoid of the large hold-time problem existing in conventional pulsed latches. According to the 7-nm FinFET postlayout simulation results, the sequencing timing overheads improved by 40% and 36% in SSPL, in comparison with the conventional MSFF at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {DD}} =0.4$ </tex-math></inline-formula> and 1.0 V, respectively. Furthermore, the hold time reduced by 54% and 58% in SSPL and at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {DD}} =0.4$ </tex-math></inline-formula> and 1.0 V, respectively, in comparison with the conventional pulsed latch.

An effective GDI (Gate Diffusion Input) Based 16- bit Shift Register Design for Power and Area Optimization

Abstract: Sequential circuit design is heavily influenced by power consumption and area reduction. Mainly consisted is shown here. Rather than using flip flops, pulsed latches are used to limit the amount of space these utilize. The shift register uses a minimal number of pulsed clock signals by combining the latches into numerous sub shifter registers and using Multiplexer and additional temporary storage latches. Multiple non-overlap delayed pulsed clock signal schemes are presented for data synchronization in a multi bit shift register to decrease power consumption. In order to maintain the current system, Tanner SEDIT will be used with Taiwan Semiconductor (TSMC) 0.18mm technology. Designing low-power digital combinational circuits using Gate Diffusion Input(GDI) is a common practice nowadays. When used in particular operating conditions, the GDI approach restores the in-cell swing by implementing sophisticated logic functions on two transistors. This method reduces power consumption, propagation latency, and digital circuit size while maintaining low complexity of logic design. Dual Edge Triggered Flip Flop(DETFF) implementation using GDI technology is introduced as an improvement to the shift register design. This idea also takes into account time restrictions, which can be reduced with the least amount of management. Keywords: Shift Register, Thermometer Code, Gate Diffusion Input, Dual Edge Triggered Flip-Flop, Propagation latency.

Comparative study of shift register using flip flop and latches

Abstract—This paper discusses a comparison of shift registers that use flip-flops and latches. In VLSI circuits, the basic building blocks are flip-flops and latches. Consider the latches and flip-flops in a shift register.As latches are the smallest circuit of flip-flops, they are used instead of flip-flops to save space and electricity. This paper compares numerous shift register approaches based on latches and flipflops. The shift register is built with numerous non overlap delayed clock pulsed latches based on the results for a more accurate manner of consuming less area and power. Multiple non overlap delayed pulsed clocks are applied to the latches to avoid the timing problem in shift registers when latches are used instead of flip- flops. Each latch is enabled by a standard 2:4 decoder. This is a good way for making a low-power, small-area shift register in a VLSI circuit. Keywords—Shift Register,Latches,Flipflop,Decoder.

Fully Synthesizable Unified True Random Number Generator and Cryptographic Core

This paper introduces a novel class of architectures that unify true random number generation and private-key cryptography by reusing the cryptographic core for both tasks. The unified architecture is well suited for low-cost constrained secure integrated systems, in view of the inherent area efficiency and the low design effort entailed by conventional automated design flows. Clock pulse over-stretching in pulsed latch clocking generates randomness by inducing metastability and jittered oscillations. Shannon confusion and diffusion in the cryptographic datapath enforce high entropy and robustness against variations. Conventional cryptographic operation is alternatively performed at moderate clock pulsewidths. A 40-nm CMOS testchip demonstrates the proposed unified architecture with a compact area of 0.43 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot 10^{6}~F^{2}$ </tex-math></inline-formula> ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$F\,\,=$ </tex-math></inline-formula> minimum feature size), based on a SIMON cryptographic core. The true random number generator (TRNG) output shows cryptographic-grade quality without any calibration across dice, process (across two manufacturing lots), voltage, and temperature variations. Energy per encryption down to 0.25 pJ/bit is demonstrated. Unification of TRNG and the cryptographic core results in inherent data locality and obfuscation of key generation within logic, improving the resilience to physical attacks.

A novel approach to design a digital clock triggered modified pulse latch for 16-bit shift register

A low power area reduced clock pulse generator and a modified clock sense pulse latch is proposed for conventional shift register. The proposed clock pulse generator basically based on the inverted inverter delay circuit and a pass transistor logic AND gate circuit. This clock pulse generator and modified clock sense pulse latch consumes low power and low area than other conventional clock pulse generator. Here the clock pulse generator consist of five number of back to back cascaded clock pulse circuit. The pulse generated from the proposed clock pulse generator helps to increase the speed, reduces the area and power of conventional shift register. The clock pulse generator and the modified clock sense pulse latch is designed and tested by the Cadence Virtuoso 180 nm technology. The power consumption for 16-bit shift register is 0.705 mW at 500 MHz clock frequency and 0.395 mW at 100 MHz frequency. The proposed shift register saved 12% area and 19.50% power rather than other conventional shift register.

A novel approach to design a digital clock triggered modified pulse latch for 16-bit shift register

A low power area reduced clock pulse generator and a modified clock sense pulse latch is proposed for conventional shift register. The proposed clock pulse generator basically based on the inverted inverter delay circuit and a pass transistor logic AND gate circuit. This clock pulse generator and modified clock sense pulse latch consumes low power and low area than other conventional clock pulse generator. Here the clock pulse generator consist of five number of back to back cascaded clock pulse circuit. The pulse generated from the proposed clock pulse generator helps to increase the speed, reduces the area and power of conventional shift register. The clock pulse generator and the modified clock sense pulse latch is designed and tested by the Cadence Virtuoso 180 nm technology. The power consumption for 16-bit shift register is 0.705 mW at 500 MHz clock frequency and 0.395 mW at 100 MHz frequency. The proposed shift register saved 12% area and 19.50% power rather than other conventional shift register.

Analysis and Design of Universal Shift Register Using Pulsed Latches

Power utilization and die region space are the significant boundaries which are considered for structuring low level power outcomes. This paper put forward the structure of low force general move register and 4-piece counter utilizing pipe rationale. Since flip failures are an innate structure hinder in a few applications, different flip lemon are over viewed and executed in widespread move register and 4-piece counter. Flip lemon utilizing pipe rationale is viewed as dependent on the correlation of intensity and region. At last, a low force all inclusive move register and 4-piece counter is planned utilizing pipe rationale. The proposed USR and 4-piece counters are mimicked with various clock rate going from 100 KHz to 500MHz. Re-enactment of these flip flounders, the widespread move register and the 4-piece counters are finished utilizing Tanner device at 180nm innovation. The normal force and the PDP of USR are improved by 33% and 27% and further the normal force and the PDP of 4-piece counter are improved by 36.9% and 30.2% when contrasted and existing plan separately. So the put forward plan is reasonable for low level power and elite applications.

Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS

Min-delay (MID) error rates increase dramatically under aggressive voltage and technology scaling, limiting VMIN. Pulsed latches offer significant clocking power savings over flip-flops but further aggravate MID failures. This letter proposes MID margin/error detection and correction (M <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /EDAC) for flip-flops and pulsed latches to reduce VMIN guard bands for voltage noise, temperature variation, and aging, and to detect and correct rare MID failures. Statistical data collection from a prototype in 10-nm tri-gate CMOS shows up to 122-mV VMIN reduction. Reliable pulsed latches enabled by M <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /EDAC offer 12%-18% total dynamic power savings for logic blocks in 10-nm CMOS.

Analysis of CNTFET Performance in Sequential Device Using Shift Register for Low Power Applications

Nanotechnology has touched the post silicon era where the MOSFET has touched its least scaling value according to Moore’s law. Further lowering in the technology nodes had bring out Short channel effects that are reflected in reliability issues to electronic components which we could visualize in our day today activities. The alternative and the best replacement for CMOS technology is Carbon Nano Tube Field Effect Transistors (CNTFET). These Carbon nanotubes because of their distinctive nature in structural, electrical and mechanical properties will be the building blocks for future Nano electronics. This work focused on design and analysis of Sequential logic devices using CNTFET and comparative analysis with CMOS performance. For Sequential device analysis, we considered Shift register as these forms the basic building block of memory devices. These devices helps in storage or in transfer of binary data. For designing Shift registers we proposed Pulsed latches rather than the regular flip-flops as they consume more power. The design has been implemented in both CNTFET and CMOS technologies for 32nm technology node. The comparative findings show that our suggested job has better Power, Delay and Power Delay Product performance.

Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time

A self-timed pulsed latch (STPL) is proposed for low $V_{\mathrm {DD}}$ operation. By comparing input and output, the transparency window is adaptively generated in STPL, which resolves the hold time problem of the conventional pulsed latch. The measurement results from the test chip fabricated in the 65-nm technology proves that the hold time is reduced by 77% and the minimum operating supply voltage is lowered by 300 mV compared with the conventional pulsed latch. In addition, the measurement results show that the STPL can reduce the sequential overhead, because the STPL is free from setup time issue from which the conventional master–slave-based flip-flop (MSFF) suffers. The simulation results show that the input-to-output delay of STPL, which also determines the sequential overhead, is smaller by 45% in 0.6 V compared with that of the MSFF structure.

Low Power Implementation of Linear Feedback Shift Registers

This paper describes low power design and implementation of Linear Feedback Shift Register (LFSR). The easiness in implementation and simple operation of Linear Feedback Shift Register have made it fit into a wide range of digital systems design. Since random pattern generation, data encryption and decryption play a major role in communication systems, the LFSR comes into view for developing the patterns for these applications. As the need increases day after day, simple and high-performance design of LFSR is required. As power consumption of the device being an important factor in the VLSI circuits, it has to be reduced by including power optimization techniques in the designs. Pulsed Latch is a popular technique of reducing power consumption which uses Pulsed Latches instead of flip-flops. As latches have lesser number of circuit elements compared to flip-flops, the area is also minimized. By implementing this pulsed latch technique, the linear feedback shift register can be designed with low power and area. The design entry is done in VHDL code and implemented using Cadence tool. In Cadence, Nclaunch, RTL Complier and Encounter tools are used for simulation, synthesis and implementation. With this method, the power reduction is achieved up to 41.99%

Near- and Sub- $V_{t}$ Pipelines Based on Wide-Pulsed-Latch Design Techniques

This paper presents a methodology and chip demonstration to design near-/sub-threshold voltage ( $V_{t}$ ) pipelines using pulsed latches that are clocked at very wide pulses. Pulsed-latch-based design is known for time borrowing capability but the amount of time borrowing is limited due to hold time constraint. To enable more cycle borrowing, in this paper, we aim to pad short paths to ~1/3 cycle time using multi- $V_{t}$ cell library. While delay padding using multi- $V_{t}$ cells is common in super- $V_{t}$ design, the small delay difference among multi- $V_{t}$ cells has not allowed such extensive short path padding due to large area overhead. However, in near-/sub- $V_{t}$ regime, circuits delay becomes exponentially sensitive to $V_{t}$ , suggesting that high- $V_{t}$ cells can significantly reduce the overhead of padding. We build a semi-automatic short path padding flow around this idea, and use it to design: 1) ISCAS benchmark circuits and 2) an 8-bit 8-tap finite impulse response (FIR) core, the latter fabricated in a 65-nm CMOS technology. The chip measurement shows that the proposed FIR core achieves 45.2% throughput (frequency), 11% energy efficiency (Energy/cycle), and 38% energy-delay-product improvements at 0.35 V over the flip-flop-pipelined baseline. The measurement results also confirm that the proposed FIR core operates with the same pulsewidth setting robustly across process, voltage, and temperature variations.

Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches

Pulsed latches are gaining increased visibility in low-power ASIC designs. They provide an alternative sequential element with high performance and low area and power consumption, taking advantage of both latch and flip-flop features. While the circuit reliability and robustness against different process, voltage, and temperature variations are considered as critical issues with current technologies, no significant reliability study was proposed for pulsed latch circuits. In this paper, we present a study on the effect of different PVT variations on the behavior of pulsed latches, considering the effect on both the pulser and the latch. In addition, two novel design approaches are presented to enhance the reliability of pulsed latch circuits, while keeping their main advantages of high performance, low power, and small area. Experiments performed using Synopsys 28nm PDK demonstrate the ability of the proposed approaches to keep the same reliability level at different supply voltages and temperatures in the presence of process variations, with a very small area overhead of around 3%. The two proposed designs have negligible power overhead when running at nominal supply voltage, and they have higher yield per unit power when compared with the traditional design at different voltages and temperatures.

Low-Complexity Shift Register Based on Decoder Enabled Pulsed Latches

Low-Complexity Shift Register Based on Decoder Enabled Pulsed Latches

&lt;italic&gt;In Situ&lt;/italic&gt; Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations

In order to achieve high tolerance against process, voltage, and temperature variations in the ultralow voltage (ULV) circuits, in situ error detection and correction (EDAC) techniques were presented. However, circuits adding the capability of error detection incur large hardware overhead, especially in ULV due to larger delay variability. In this paper, we analyze the hardware overhead of error detection techniques in pipelines based on three different sequential elements: flip-flops, two-phase latches, and pulsed latches. By exploiting the cycle-borrowing ability, we propose a technique called sparse insertion of error detecting registers on the two-phase latch-based and pulsed-latch-based pipelines to reduce the sequential logic area. Furthermore, we propose a delay-padding methodology using a multi- $V_{t}$ cell library in ULV circuits to reduce EDAC hardware overhead. The proposed techniques are applied on a benchmark six-stage pipeline operating at 0.35 V in a 65-nm CMOS. The analysis results show that our proposed techniques can reduce the total area by 26%–33% and the error detecting register count by 2.9– $4.3\times $ compared with conventional EDAC techniques.

Pulsed Latches Methodology to Attain Reduced Power and Area Based On Shift Register

The power consumption and area reduction are the key challenges in the Very Large Scale Integration (VLSI) circuit design. Power consumption and Area reduction plays a major role in sequential circuit design. Shift register is the main building block in the VLSI circuits. The shift register is composed of clock inter connection network and timing elements such as flip-Flops and latches. The shift registers are design using edge triggered flip flops but the use of latches for shift register design also optimizes the area. This project introduces a low power and area efficient shift register using pulsed latch and pulse generation circuit. If the Flip-Flop is replaced with the pulsed latch the area and power consumption can be reduced to 50% in the shift register. For this design a non overlap clock pulses are used. This solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. To minimize power consumption various non overlap delayed pulsed clock signal design is proposed for data synchronization in an exceedingly multi bit shift register. The proposed system is designed by using a popular Schematic and layout capture tool with 90nm technology.