Near- and Sub- $V_{t}$ Pipelines Based on Wide-Pulsed-Latch Design Techniques

Abstract

This paper presents a methodology and chip demonstration to design near-/sub-threshold voltage ( $V_{t}$ ) pipelines using pulsed latches that are clocked at very wide pulses. Pulsed-latch-based design is known for time borrowing capability but the amount of time borrowing is limited due to hold time constraint. To enable more cycle borrowing, in this paper, we aim to pad short paths to ~1/3 cycle time using multi- $V_{t}$ cell library. While delay padding using multi- $V_{t}$ cells is common in super- $V_{t}$ design, the small delay difference among multi- $V_{t}$ cells has not allowed such extensive short path padding due to large area overhead. However, in near-/sub- $V_{t}$ regime, circuits delay becomes exponentially sensitive to $V_{t}$ , suggesting that high- $V_{t}$ cells can significantly reduce the overhead of padding. We build a semi-automatic short path padding flow around this idea, and use it to design: 1) ISCAS benchmark circuits and 2) an 8-bit 8-tap finite impulse response (FIR) core, the latter fabricated in a 65-nm CMOS technology. The chip measurement shows that the proposed FIR core achieves 45.2% throughput (frequency), 11% energy efficiency (Energy/cycle), and 38% energy-delay-product improvements at 0.35 V over the flip-flop-pipelined baseline. The measurement results also confirm that the proposed FIR core operates with the same pulsewidth setting robustly across process, voltage, and temperature variations.