Short path padding with multiple-V<inf>t</inf> cells for wide-pulsed-latch based circuits at ultra-low voltage

Abstract

This paper presents a short path padding technique for wide-pulsed-latch based circuit design in near/sub-threshold (V t ) regime. To reduce the additional hardware cost, multiple-V t buffer cells are used to pad the short paths to avoid hold time violations. To reduce the runtime of the padding algorithm further, step-by-step based and path group based short path padding schemes are proposed. Employing the integer linear programming (ILP) solver, an automatic short path padding software is developed. Experimental results show that our proposed short path padding technique can reduce 52.3% hardware padding cost on average. Furthermore, the runtime of padding software is reduced 79.6%, 74.95% and 80.88%, by using the step-by-step based, path group based and the hybrid scheme, respectively. In consequence, this technique supports up to a wide pulse of 1/3 cycle time in the pulsed-latch pipelines to enable a large time-borrowing capability and tolerance of variations.