Design of a Highly Reliable and Reconfigurable Pulsed Latch Circuits

Abstract

Pulsed latches are the most important storage elements used in many VLSI circuits, due to their low area and power consumption. The pulsed latch circuit consists of a pulse generation circuit, which generates a pulsed clock signal and is given to its corresponding latches. Among different latches namely Modified Hybrid Pulsed Latch (MHLFF), Transmission Gate Pulsed Latch (TGPL), and Static Differential Pulsed Latch (SSASPL), the SSASPL has low power and delay and is used in all designs. The traditional pulse generation circuit used for the generation of the pulsed clock signal does not work well under different process, voltage and temperature (PVT) variations, so the reliability level is very less for these circuits. To enhance the reliability, two novel design approaches namely Header switch based pulsed latch (PL_SW) and MUX-based pulsed latch (PL_MUX) are designed and compared with the traditional pulsed latch in TANNER EDA tool using 180 nm technology.