Design & Benchmark of Single Bit & Multi Bit Sequential Elements in 65nm for Low Standby Power Consumption

Abstract

In the present scenario, the power consumed by the clock tree network is one of the significant issues for large scale digital integrated circuits. One way to decrease the power consumption, and the area of the sequential elements, is to move from flip flop (FF) to pulsed latch. The pulsed latch circuit can be divided in two parts, first is a latch circuit, and the second is a pulse generator circuit. The pulse generator can be shared across different latches for lesser power consumption and area. While sharing the clock buffer of different latches, their position in the design needs to be changed. Due to this, the performance of the original design may get affected. This paper shows the designing and characterization of a flip flop and a pulsed latch. A conventional Master-Slave Flip Flop (MSFF) is designed, and for lower power consumption MTCMOS technique is used. A single bit pulsed latch is designed, and from it, a nibble (four-bit) pulsed latch is derived, by sharing the pulse generator with other latches. The main objective is to focus on advantages that can be achieved by moving from a single bit to a multi-bit sequential element in terms of power, performance, and area (PPA). The maximum dynamic power, leakage charge, Power Delay Product, and area consumption can be reduced by 37.38%, 67%, 57.23%, and 42.81%, respectively, if we move towards multi-bit sequential elements. The designing of the flip flop and pulsed latch is done in 65 nm Low Standby Power CMOS technology at 1V and 500 MHz clock frequency.