Pulse-triggered Flip-flop Research Articles

A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design

A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design

Design of Pulse-Triggered Flip-Flop

Design of Pulse-Triggered Flip-Flop

Low power pulsed flip-flop with clock gating and conditional pulse enhancement

A clock system consumes above 25% of the total system power. Flip-flops (FFs) are widely used as the basic storage element in all kinds of digital structures. The use of pulse-triggered flip-flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. Two important features are embedded in this flip-flop architecture. Firstly, the enhancement in width and height of trigger pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90 nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs. This paper also presents a comparative study on the performance of implicit and explicit pulse flip-flop designs. The maximum power saving of proposed design against conventional implicit and explicit design is up to 18.45% and 58.49%, respectively.

Low power pulsed flip-flop with clock gating and conditional pulse enhancement

A clock system consumes above 25% of the total system power. Flip-flops (FFs) are widely used as the basic storage element in all kinds of digital structures. The use of pulse-triggered flip-flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. Two important features are embedded in this flip-flop architecture. Firstly, the enhancement in width and height of trigger pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90 nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs. This paper also presents a comparative study on the performance of implicit and explicit pulse flip-flop designs. The maximum power saving of proposed design against conventional implicit and explicit design is up to 18.45% and 58.49%, respectively.

A Highly Efficient Conditional Feedthrough Pulsed Flip-Flop for High-Speed Applications

A novel type of highly efficient conditional feedthrough pulse-triggered flip-flop (P-FF) is proposed and demonstrated. The data-to-output (D-to-Q) delay in this circuit was highly optimized using predischarging and conditional signal feedthrough schemes. Power consumption was also reduced using a shared pulse generator and an output feedback-controlled conditional keeper, which diminished the floating status of the internal node. The driving strength of this design was further enhanced by including an additional pull-down path at the output node. Various postlayout simulation results applied to 16-nm FinFET technology demonstrated a higher energy efficiency (at all input data toggle rates) for the proposed topology than comparable P-FF devices. Notably, the proposed model achieved a 62% D-to-Q delay reduction, compared to a transmission gate FF, outperforming the device by more than 66% in terms of power efficiency and 87% in energy efficiency (at a 50% input data toggle rate). Improvements were even more significant in comparison with other conventional P-FFs. These results suggest the proposed design to be a viable new option for high-efficiency sequential elements in high-speed applications.

Effect of clock gating in conditional pulse enhancement flip-flop for low power applications

Flip-Flops (FFs) play a fundamental role in digital designs. A clock system consumes above 25% of total system power. The use of pulse-triggered flip-flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. This flip-flop architecture is embedded with two key features. Firstly, the enhancement in width and height of triggering pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90-nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs. Its maximum power saving against conventional designs is up to 30.65% .

Ultra-Low Power Pulse-Triggered CNTFET-Based Flip-Flop

Reducing the power consumption and scaling the devices are the important concerns of today's electronics. Flip-Flop (FF) is one of the basic elements in electronic devices. Thus, the performance of the electronic devices is improved by improving these qualities in the FFs. In this paper, a novel pulse-triggered CNTFET-based D-Flip-Flop structure is proposed. This structure utilizes signal feed through technique to reduce the “0” to “1” transition, which requires only one CNTFET. Moreover, the discharging path is optimized to reduce the delay time for “1” to “0” transition by using only two CNTFETs. The novel structure is simulated in Hspice using Stanford model. The output results prove that the performance of the proposed structure is improved greatly in terms of power consumption, D-to-Q delay, the power-delay product, and the number of required transistors in comparison with other pulse-triggered Flip-Flop structures.

Low power aware pulse triggered flip flops using modified clock gating approaches

PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.FindingsThe design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.Originality/valueThe study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.

Implementation of MHLFF based low power pulse triggered flip flop

The present research paper proposes to implement a low power pulse-triggered flip-flop. The proposed design is MHLFF (modified hybrid latch flip-flop). In MHLFF method, the pulse generator will be altered concerning illustration inverters what’s more a pasquinade transistor. This technique will be comparative should understood kind about flip flop what’s more it utilizes a static lock structure. Should succeed Most exceedingly bad situation delay issue brought on Eventually Tom's perusing discharging way comprise from claiming three stacked transistor MHLFF may be presented. We can minimize the power and delay when compared to the existing models i.e, CDFF and SCDFF. The circuit was implementing using Cadence Virtuoso tool in 90-nm and 45-nm technology.

Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI

In this paper, we propose pulse-triggered flip-flops (pulsed-FF) and register file in 28nm Ultra-Thin-Body-and-Box Fully-Depleted-Silicon-on-Insulator (UTBB-FDSOI) technology, dedicated to ultra-wide voltage range (UWVR) operation. A pulsed-FF composed of a latch and a pulse generator offers potential power/performance/area (PPA) advantages over the conventional master-slave flip-flop. A comparative study of 6 different latch topologies, in the energy-delay (E−D) space, points out the most efficient architectures. Furthermore, we demonstrate that the tuning capability based on the wide MOSFET back biasing range available in UTBB-FDSOI allows to cover the whole (E−D) space with a single sizing. For the pulse generation, we propose a new delay generator to guarantee the robustness at ultra-low voltage (ULV), down to 0.35V. The PPA and robustness improvement of the proposed pulsed-FF are demonstrated by silicon measurements, and its tuning capabilities based on back biasing are discussed. Finally, a register file based on the proposed pulsed-FF is reported with a pulse generator (PG) sharing technique, showing 28% and 72% (@Vdd=1V) improvements in area and energy-delay product, respectively, compared to its master–slave counterpart.

Design and analysis of Low Power High Speed Pulse Triggered Flip Flop

The main important aspect is to outline a high speed and utilization of low power pulse triggered flip-flop and simulate the same. Also, we have to minimize leakage in the consumption of power in a flip-flop by employing pulse triggering technique that is adopted for clocks. Here, to solve the problem in the discharging path of the similar flip flop implementations, we employ signal feed through technique. The discharge time is reduced by the proposed method. This design out performs all the other similar pulse triggered flip flop implementation both in speed and power consumption. Now, it is implemented by employing Cadence Virtuoso Schematic Composer in 90nm GPDK. Simulation is done by a simulator known as Spectre.

Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme

A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS) is proposed, which employs a transmission-gate-logic (TGL) based clock-gating scheme in the pulse generation stage. This scheme condi- tionally disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated, leading to low power efficiency. Based on SMIC 65 nm technology, extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption, compared with its counterparts at 10% data-switching activity. Also, full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus, DIFF-CGS is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities.

Low Power Area Efficient VLSI Architectures for Shift Register Using Explicit Pulse Triggered Flip Flop Based on Signal Feed-Through Scheme

Low Power Area Efficient VLSI Architectures for Shift Register Using Explicit Pulse Triggered Flip Flop Based on Signal Feed-Through Scheme

Asynchronous Model of Flip-Flop’s and Latches for Low Power Clocking

There is a wide selection of flip-flops in the literature. Many contemporary microprocessors selectively use master-slave and pulsed-triggered flip-flops. Transmission gated flip-flop, are made up of two stages, one master and one slave Alternatively, pulse-triggered flip-flops reduce the two stages into one stage and are characterized by the soft edge property. The concepts discussed in the related work are related to synchronous design’s novel method for low power dissipation asynchronous methods have been improving so as to reduce the power consumption an asynchronous methods for flip-flops are being implemented.

LOW-POWER HIGH PERFORMANCE PULSE-TRIGGERED FLIP-FLOP

In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. First, the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple twotransistor AND gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various post layout simulation results based on UMC CMOS 90- nm technology reveal that the proposed design features the best power-delay-product performance in seven FF designs under comparison. Its maximum power saving against rival designs is up to 38.4%. Compared with the conventional transmission gate-based FF design, the average leakage power consumption is also reduced by a factor of 3.52.

Design and Implementation of 4 Bit Static RAM through Low-Power Pulse-Triggered Flip-Flop

Design and Implementation of 4 Bit Static RAM through Low-Power Pulse-Triggered Flip-Flop

Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique

Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.

DESIGN OF LOW POWER AND HIGH PERFORMANCE PULSE TRIGGERED FLIP FLOP USING CONDITIONAL PULSE ENHANCEMENT METHOD

In this paper, a novel low-power high performance pulse-triggered flip-flop using conditional pulse enhancement design method is presented. Our proposed design is Enhanced Pulse Triggered Low-power Flip Flop (EPTLFF). It design is done by the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. The EPTLFF avoids unnecessary internal node transitions to reduce power consumption. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various layout simulation results comparison between previously reported design and modified design is based on 90nm and 50nm technology. The proposed design features the best power-delay-product performance in five FF designs under comparison. Its maximum power saving compared to the conventional P-FF designs is up to 18.6%.

IJIREEICE - Electrical, Electronics, Instrumentation and Control

A low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Based on post-layout simulation results using cadence virtuoso CMOS 180-nm technology, the proposed design outperforms the conventional P-FF design. The proposed design features the best power-delay-product performance in both implicit and explicit type flip flops under comparison. Counters can be designed using such flip flop. As a result power consumption is reduced compared to conventional methods. In this paper, a low power explicit pulse triggered flip flop is discussed as a proper choice of low power applications and comparison with other flip flop architectures.

A Novel Approach For Design Of Pulse Triggered Flip-Flop To Enhance Speed And Power

In VLSI Technology, flip-flops contribute a significant portion of chip area and power consumption to overall system design. Pulse triggered flip-flops (P-FF) have single latch and hence simpler in circuit complexity. Use of Explicit type design for P-FF gives the speed advantage. This paper presents various Pulse triggered Flip-flop (P-FF) designs and various techniques to achieve a better design in terms of power consumption and speed. Introduction of simple pass transistor in latch design can be used to speed up data transition. Dual edge triggering can be adopted as it consumes less power as compared to single edge triggering. Also conditional discharge technique can be used to reduce switching activity. The work is done in tanner tool software. KeywordsFlip-Flop, Pulse Triggered, Dual Edge __________________________________________________*****_________________________________________________