Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI

Abstract

In this paper, we propose pulse-triggered flip-flops (pulsed-FF) and register file in 28nm Ultra-Thin-Body-and-Box Fully-Depleted-Silicon-on-Insulator (UTBB-FDSOI) technology, dedicated to ultra-wide voltage range (UWVR) operation. A pulsed-FF composed of a latch and a pulse generator offers potential power/performance/area (PPA) advantages over the conventional master-slave flip-flop. A comparative study of 6 different latch topologies, in the energy-delay (E−D) space, points out the most efficient architectures. Furthermore, we demonstrate that the tuning capability based on the wide MOSFET back biasing range available in UTBB-FDSOI allows to cover the whole (E−D) space with a single sizing. For the pulse generation, we propose a new delay generator to guarantee the robustness at ultra-low voltage (ULV), down to 0.35V. The PPA and robustness improvement of the proposed pulsed-FF are demonstrated by silicon measurements, and its tuning capabilities based on back biasing are discussed. Finally, a register file based on the proposed pulsed-FF is reported with a pulse generator (PG) sharing technique, showing 28% and 72% (@Vdd=1V) improvements in area and energy-delay product, respectively, compared to its master–slave counterpart.