Abstract
Flip-Flops (FFs) play a fundamental role in digital designs. A clock system consumes above 25% of total system power. The use of pulse-triggered flip-flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. This flip-flop architecture is embedded with two key features. Firstly, the enhancement in width and height of triggering pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90-nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs. Its maximum power saving against conventional designs is up to 30.65% .
Highlights
In all kinds of digital structures flip-flops are widely used as the basic storage element
The post layout simulations of all pulse-triggered flipflops (P-FFs) are done in cadence by using CMOS 90nm technology
From the simulation result it is clear that the power consumption and power-delay-product (PDP) performance of proposed Clock gated conditional pulse enhancement flip-flop (CGCPEFF) outperforms single-ended conditional capturing energy recovery FF (SCCERFF) and conditional pulse enhancement FF (CPEFF) due to the embedding of conditional pulse enhancement technique and the clock gating concept, with slight overhead in delay and area
Summary
In all kinds of digital structures flip-flops are widely used as the basic storage element. The single latch structure design of PFFs made them more popular than conventional master-slave and transmission gate-based FF designs in low power and high-speed applications [3]. The sharing of pulse generator among neighboring latches is an advantage of explicit P-FF Both implicit and explicit P-FFs face the longest discharging path problem in the latch structure. This increases the size of the transistors used at the pulse generator to enlarge the width and height of triggering pulses for the sufficient capturing of data. A low power P-FF is presented which has an implicit style of operation This structure solves the longest discharging path problem in the latch and unwanted switching activities at sleep/idle mode of operation.
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