Pulse Counters Research Articles

Performance of Active-Quenching SPAD Array Based on the Tri-State Gates of FPGA and Packaged with Bare Chip Stacking.

The performance of an active-quenching single-photon avalanche diode (SPAD) array that is based on the tri-state gates of a field programmable gate array (FPGA) is presented. The array is implemented by stacking a bare 4 × 4 N-on-P SPAD array on a bare FPGA die, and the electrodes of the SPAD pixels and the I/O ports of the FPGA are connected through wire bonding within the same package. The active quenching action on each SPAD pixel is performed by using the properties of the tri-state gates of the FPGA. Digital signal processing, such as pulse counters, data encoders, and command interactions, is also performed by using the same FPGA. The breakdown voltage of the SPAD pixels, with an active area of 60 μm × 60 μm, is 47.2-48.0 V. When the device is reverse biased at a voltage of ~50.4 V, a response delay of ~50 ns, a dead time of 157 ns, a dark count rate of 2.44 kHz, and an afterpulsing probability of 6.9% are obtained. Its peak photon detection probability (PDP) reaches 17.0% at a peak wavelength of 760 nm and remains above 10% at 900 nm. This hybrid integrated SPAD array is reconfigurable and cost effective.

A 64 × 64 SPAD-Based Indirect Time-of-Flight Image Sensor With 2-Tap Analog Pulse Counters

This article presents a 64 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 64 indirect time-of-flight (iToF) image sensor with a depth range of 50 m, integrated into a 1P4M 110-nm CMOS process. The sensor is based on a single-photon avalanche diode (SPAD), the range-dependent phase delay of which is measured by compact analog time-gated pulse counters and then read out by column-parallel single-slope (SS) analog-to-digital converters (ADCs). We present two prototypes of iToF sensors that exploit one- or two-tap counters in the pixel. Compared to the one-tap sensor, the two-tap sensor achieves an improved fill factor of 26.3% with a pixel pitch of 32 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text {m}$ </tex-math></inline-formula> . This improvement is realized by using a retrograde deep n-well as guard-ring structure and two analog counters whose layout has been optimized. By utilizing two different demodulation frequencies of 1.56 and 50 MHz, the two-tap sensor achieves a large depth range of 50 m with a relative depth uncertainty of 0.22% and a high 3-D frame rate of 65 frames/s. When using an optical bandpass filter and multi-frame accumulation, the sensor shows a tolerance of 120-klx sunlight. Compared with the previous iToF benchmarks, the proposed SPAD-based iToF sensor demonstrates the largest depth range without compromising the relative depth uncertainty.

Analysis and design of low power wideband programmable frequency divider in 0.13-μm SiGe BiCMOS technology

In this paper, a newly analytical method is proposed for the design of programmable frequency dividers. The more accurate transfer function of the current mode logic (CML) stage is used to analyze the injection-locking behavior models of the dual-modulus prescaler, and the general analytical expressions of the locking range of the prescaler are derived. Based on the analytical expressions that can be calculated using device-level circuit parameters obtained through DC and AC simulations, the dual-modulus prescaler design can be optimized quickly and accurately, thereby extending the frequency-division range of the programmable frequency divider. The proposed analytical method is verified by the measured results of the 2–22 GHz programmable divider, fabricated in 0.13-μm SiGe BiCMOS technology. By using heterojunction bipolar transistors (HBTs) in the dual-modulus prescaler and metal–oxidesemiconductor field-effect transistors (MOSFETs) in the pulse and swallow counters, the proposed programmable divider achieves the lowest power consumption of 63.3 mW and the best FOMT compared with previously works.

Fabrication of 3-Layer Stacked Pixel for Pixel-Parallel CMOS Image Sensors by Au/SiO2 Hybrid Bonding of SOI Wafers

CMOS image sensors have improved their performances including pixel counts, frame rate, and dynamic range to meet the rising demands for high-quality video systems such as 8K/4K television [1] and three-dimensional (3D) imaging. In recent days, 3D integration technologies have been utilized in CMOS image sensor fabrication by using mainly through-silicon vias (TSVs) [2-3]. However, TSVs are shared by plural pixels, thereby preventing fully parallel signal processing to limit sensor performance in conventional stacked sensors. This is because the TSV penetrates the pixel area and it is difficult to be integrated within pixel.To overcome this problem, we have proposed a 3D integration technology without using TSVs but Au/SiO2 hybrid bonding of silicon-on-insulator (SOI) wafers. Stacked layers are electrically connected with Au electrodes integrated in every pixel, which gives pixel-parallel signal processing to image sensor as illustrated in Fig. 1, where Au electrodes are embedded in the SiO2 intermediate layer by the damascene process with chemical mechanical polishing (CMP). The electrode size can be reduced to 1 μm or less in diameter. We previously developed 2-layer stacked pixel-parallel image sensor and showed its wide dynamic range with the ability to capture video images [4-6]. In this paper, we report 3-layer stacked image sensor pixel by extending the 3D integration technology, aiming to shrink the pixel size and to enhance functionality of the pixel-parallel image sensor.Figure 2 shows the fabrication process for the 3-layer stacked CMOS image sensor. The top layer is assigned for photo-detectors and pulse generation circuits, where number of generated pulses are designed to correspond to input illuminance. The middle and bottom layers are for the lower and upper 8-bit pulse counters, respectively. The 3-layer configuration gives every pixel a 16-bit A/D conversion function. The fabrication process flow is as follows: (1) The intermediate SiO2 layers of the top and middle layer equipped with photo detectors or integrated circuits are patterned and etched to form via holes, and the Au electrodes are embedded by electroplating and CMP. (2) The two layers are directly bonded at room temperature mediated with Si thin layer [7]. (3) The handle layer of the middle layer is removed by grinding and XeF2 vapor phase etching, and the backside Au electrodes are formed in the same process as (1). (4) The bottom layer equipped with integrated circuits is then bonded by the same manner as the first bonding, and finally the handle layer of the top layer is removed. By repeating the bonding, electrode forming, and handle layer removing processes, we could obtain multi-layer devices more than three.The cross-sectional SEM image for the developed 3-layer stacked 8-inch wafer is shown in Fig. 3, where no void or separation was observed at the bonded interfaces. The electrode size was 5 μm in diameter with alignment accuracy of as good as 1 μm. Figure 4 shows the measured input-output characteristics of the developed 3-layer stacked pixel. We confirmed linear response of 16-bit digital signal output from pulse counters in middle and bottom layers, which indicates the developed sensor pixel has high bit depth and wide dynamic range with excellent linearity.In summary, a 3-layer stacked pixel for pixel-parallel CMOS image sensor was developed by using hybrid bonding of SOI wafers and embedded Au electrodes. The developed pixel confirmed its pixel-parallel 16-bit A/D conversion operation. Our multi-layer stacked process is promising not only for image sensors with ultimate performances but also various More-than-Moore type devices with multi functions.

Superconducting nanowire multi-photon detectors enabled by current reservoirs

Single-photon detectors are ubiquitous devices in quantum-photonic-based communication, computation, metrology, and sensing. In these applications, N -fold coincidence photon counting is often needed, for example, to characterize entanglement. However, N -fold coincidence photon counting typically requires N individual single-photon detectors and associated bias and readout electronics, and these resources could become prohibitive if N goes large and the detectors need to work at cryogenic temperatures. Here, to break this limit on N , we propose a device architecture based on N cascaded photosensitive superconducting nanowires and one wider nanowire that functions as a current reservoir. We show that by strategically designing the device, the network of these superconducting nanowires can work in a synergic manner as an n -photon detector, where n can be from 1 to N , depending on the bias conditions. We therefore name the devices of this type superconducting nanowire multi-photon detectors (SNMPDs). In addition to its simple one-port bias and readout circuitry, the coincidences are counted internally in the detector, eliminating the need for external multi-channel, time-correlated pulse counters. We believe that the SNMPDs proposed in this work could open avenues towards conveniently measuring high-order temporal correlations of light and characterizing multi-photon entanglement.

(Invited) Pixel-Parallel 3-D Integrated CMOS Image Sensors for Next-Generation Video Systems

Performances of image sensors including pixel counts, capturing speed, and dynamic range continue improving to meet the demands for high-reality video systems such as 8K/4K television and three-dimensional (3-D) imaging. Recent 3-D integration technology of silicon device has boosted sensor performances by using through-silicon vias (TSVs) and micro-bumps [1-2]. However, fully parallel signal processing has not been possible yet because the size of TSVs or micro-bumps is larger than the imaging pixel. We have proposed a new 3-D integration technology without using TSV or micro-bumps but by using direct bonding of silicon-on-insulator (SOI) wafers, in which gold electrodes are embedded in the SiO2 intermediate layer. The gold electrodes formed by the damascene process with chemical mechanical polishing (CMP) can be reduced to 1 μm or less in diameter. This 3-D integration technology enables us to develop pixel-parallel 3-D integrated CMOS image sensors [3-5] as illustrated in Fig. 1. Two SOI wafers are stacked and directly connected by the embedded gold electrodes within every pixel. We have also developed novel in-pixel A/D converters (ADCs) with pulse frequency output, where signal charges generated in photodiodes (PDs) are converted into pulse signals at a frequency corresponding to the input illuminance. The ADC has an advantage of wide dynamic range of illuminance because the signal charge accumulated in the PD is never saturated in principle. Prototype sensors of 128 × 96 resolution were developed with 80-μm square pixel each and 10-μm diameter gold electrodes. The upper layer was assigned for the PDs and ADCs, and the lower was for the 16-bit pulse counters. The two wafers were bonded by an image recognition of infra-red camera, where we achieved alignment accuracy as high as 1 μm or better. We evaluated the sensor and confirmed an excellent linear output with a wide dynamic range of 96 dB, which corresponds to the 16-bit output of the pulse counter. Fig. 2 shows an example image captured by the developed sensor. We successfully demonstrated the operation of the pixel-parallel sensor without any pixel defects. In summary, a pixel-parallel 3-D integrated CMOS image sensor with pulse-frequency-output A/D converters was developed by using direct bonding of SOI wafers and embedded gold electrodes. The developed process is promising for image sensors with ultimate performances and various More-than-Moore type devices.

A High Count Rate Neutron Beam Monitor for Neutron Scattering Facilities

Beam monitors are an important diagnostic tool in neutron science facilities. Present beam monitors use either ionization chambers in integration mode, which are slow and have no timing information, or pulse counters which can easily be saturated by high beam intensities. At high flux neutron scattering facilities, neutron beam monitors with very low intrinsic efficiency (10-5) are presently selected to keep the counting rate within a feasible range, even when a higher efficiency would improve the counting statistics and yield a better measurement of the incident beam. In this work, we report on a high count rate neutron beam monitor. This beam monitor offers good timing with an intrinsic efficiency of 10-3 and a counting rate capability of over 1,000,000 cps without saturation.

Computational design of synthetic regulatory networks from a genetic library to characterize the designability of dynamical behaviors

The engineering of synthetic gene networks has mostly relied on the assembly of few characterized regulatory elements using rational design principles. It is of outmost importance to analyze the scalability and limits of such a design workflow. To analyze the design capabilities of libraries of regulatory elements, we have developed the first automated design approach that combines such elements to search the genotype space associated to a given phenotypic behavior. Herein, we calculated the designability of dynamical functions obtained from circuits assembled with a given genetic library. By designing circuits working as amplitude filters, pulse counters and oscillators, we could infer new mechanisms for such behaviors. We also highlighted the hierarchical design and the optimization of the interface between devices. We dissected the functional diversity of a constrained library and we found that even such libraries can provide a rich variety of behaviors. We also found that intrinsic noise slightly reduces the designability of digital circuits, but it increases the designability of oscillators. Finally, we analyzed the robust design as a strategy to counteract the evolvability and noise in gene expression of the engineered circuits within a cellular background, obtaining mechanisms for robustness through non-linear negative feedback loops.

Laser vs. settling velocity differences in silt grainsize measurements: estimation of palaeocurrent vigour

AbstractThe use of grain‐size distribution of muds for the reconstruction of past deep ocean currents is becoming established and applied in the palaeoceanographic community. The methods are also applicable to shallow marine and tidal flat muds with similar inferences concerning the energy of wave and current sorting being drawn. Fine sediment grain‐size distributions can be obtained using a variety of instruments based on fundamentally different theoretical principles. These machines may give varying, sometimes misleading, results giving divergent interpretations of flow speed history. The new evidence presented here, combined with earlier work, suggests that of the three most commonly used analytical methods for fine silts with clays, settling velocity (Sedigraph) should be the method and instrument of choice, with electrical resistance pulse counters (e.g. Coulter Counter) as a suitable alternative. The data also show that laser particle sizers should be avoided for palaeocurrent reconstructions because the measured size of platey minerals can be dominated by their large projected area. This causes them to be recorded as the same size as larger equant grains although they have much smaller settling velocity and were deposited in aggregates. This produces results with a weaker relationship to the dynamics of deposition. The central problem is thus that some coarse clay/fine silt is recorded as medium to coarse silt, the key size in the ‘sortable silt’ mean size method of inferring changes in flow speed. For coarse silts (e.g. loess) the laser gives more satisfactory results.

1P1-C30 分散リアルタイム制御用M-RMT Processorの設計

In this paper, Motion Responsive MultiThreaded Processor (M-RMTP) for distributed real-time control is designed. The M-RMTP integrates many functions into an ASIC chip, such as Responsive Multithreaded Processing Unit (RMT PU), Responsive Link for real-time communication, and many peripheral functions including DDR SDRAM I/Fs, DMAC, PCI-X, IEEE1394, Ethernet, RS-232C, PWM generators, PWM inputs, pulse counters, and SPI, to control various electronic control systems. System designers can use various on-chip functions easily by connecting required I/Os to the M-RMTP. The designers can realize a distributed real-time control system by connecting several M-RMTPs with their own functions via Responsive Links.

Responsive Multithreaded Processor for Distributed Real-Time Systems

The Responsive MultiThreaded (RMT) Processor is a system LSI that integrates almost all functions for parallel/distributed real-time systems including robots, intelligent rooms/buildings, ubiquitous computing systems, and amusement systems. Concretely, the RMT Processor integrates real-time processing (RMT Processing Unit), real-time communication (Responsive Link II), computer I/O peripherals (DDR SDRAM I/Fs, DMAC, PCI-X, USB2.0, IEEE1394, etc.), and control I/O peripherals (PWM generators, pulse counters, etc.). The RMT Processor, with a design rule of 0.13&lt;I&gt;μ&lt;/I&gt;m CMOS Cu 1P8M and a die size 10.0mm square, was fabricated by TSMC. The RMT Processing Unit (RMT PU) executes eight prioritized threads simultaneously using fine-grained multithreading based on priority, called the RMT architecture. Priority of real-time systems is introduced into all functional units, including cache, fetch, and execution, so the RMT PU guarantees real-time execution of prioritized threads. If resource conflicts occur at functional units, higher priority threads overtake lower priority threads. Flexible powerful vector operation units for multimedia processing are also designed. System designers use on-chip functions easily by connecting required I/Os to this chip and the designers realize distributed control by connecting several RMT Processors with their own functions via Responsive Link II.

Design Concept of Responsive Multithreaded Processor for Distributed Real-Time Control

This paper describes the design concept of Responsive MultiThreaded (RMT) Processor for distributed real-time control that controls various embedded systems including robots, home automation, factory automation, etc. RMT processor integrates an 8-way multithreaded processor (RMT processing unit) for real-time processing, four sets of Responsive Link II for real-time communication, and I/O peripherals including DDR SDRAM I/Fs, DMAC, PCI64, USB2.0, IEEE1394, PWM generators, pulse counters, etc., into an ASIC chip. System designers can use various on-chip functions easily by connecting required I/Os to this chip directly. The designers can also realize distributed control systems by connecting several RMT processors with their own functions via Responsive Link II.

Doppler velocimeter for monitoring groundwater flow

Groundwater velocity and direction of flow are determined by insertion into borehole below the water table of a sound source and a plurality of sound sensors. A periodic sound signal is emitted by the sound source, which is submerged in groundwater at the bottom of the borehole. The sound signals are sensed by the sound sensors, which are also submerged in the water in the vicinity of the sound source. Owing to the Doppler effect, there is a shift in the frequency of the sound signals observed by the different sound sensors. The differences in frequency are determined by pulse counters and used to compute the components of groundwater velocity along north-south and east-west axes. The velocity of groundwater flow and its direction are determined by vector addition of the groundwater velocity components. These computational processes are carried out by an appropriately programmed microprocessor.

Design and Implementation of Responsive Processor for Parallel/Distributed Control and Its Development Environments

In this paper, Responsive Processor for parallel/distributed real-time processing, which can control various electronic control systems, is designed and implemented. Responsive Processor is integrates many functions into an ASIC chip, such as a RISC processing core (SPARC), Responsive Links that realize realtime communication, many peripheral functions including SDRMI/Fs, DMAC, PCI, USB, SIO, PIP, timers, pulse counters, PWM generators, A/D converters, D/A converters, etc. Its control boards and development environments are also designed and implemented.

Arithmetical measurements of electrical intensities with electro-optical devices

We describe a device measuring directly intensities up to 10 -12 A as numbers of electron charges per unit time. The high level of development of fast pulse counters and photomultipliers makes it now easy to design such devices.

Skin photoplethysmography — a review

The photoplethysmograph has been used for over 50 years but there are still misconceptions in how and what is the information obtained. A photoplethysmograph signal from any site on the skin can be separated into an oscillating (a.c.) and a steady-state (d.c.) component, their amplitudes dependent upon the structure and flow in the vascular bed. Many simple applications are available: pulse counters, using the a.c. component, skin colour and haemoglobin saturation meters, using the d.c. component. The d.c. component of the photoplethysmograph signal is a function of the blood flux beneath the device. A good emitter for use in a photoplethysmograph of skin blood flow is one in the frequency range 600–700 nm and the best signal for a.c. analysis is obtained from the finger pulp. The frequency range of the electronic circuitry should be from 0.01 to 15 Hz, then all the information in the signal can be extracted about the autonomic nervous system control of the cardiovascular system, particularly between 0.01 and 2 Hz. Comparative studies may be drawn between similar skin sites on a subject or between subjects if the afferent inputs to the brain stem are controlled or driven at a known frequency. These afferents, inputs, will modulate the efferents, outputs, which generate variations in the a.c. component of the detected photoplethysmograph signal.

Measurement of FM-signal frequency deviation by using pulse counters

Measurement of FM-signal frequency deviation by using pulse counters

Simulation and information assessment of TEM and STEM images

Small and moderate digital systems, especially those with computer-microscope interface capabilities and possibly equipped with image frame stores, are being commonly employed in electron microscopy laboratories. The complexity of such systems varies greatly, ranging from those composed of simply a personal computer with minimum interfacing hardwares such as digital to analog converters(DACs) and pulse counters (or ADCs), compact enough to be fitted into a small cart and transported from room to room, to those consisting of image processing systems controlled by mini- or super mini-computers with system-bus interface for massive data transfer, array processors for fast online data handling. Be it simple or complex, such a system allows signals from various sources to be collected and stored in digital form for on-line or off-line manipulation. Fig.1 is a highly schematic diagram of the system currently working in ASU HREM laboratory, on which this work was done.

A Microprocessor Controlled Thermoluminescence Dosemeter Reader for Routine Use and Research

A modified version of the Harshaw model 2000 TLD reader, extended with an automatic sample changer device and a microprocessor for system control and data processing is described. Using a charge-to-pulse converter for luminescence registration and two fast pulse counters, which are connected in turn, glow curve recording with high resolution has been achieved. Due to the great versatility provided by the microprocessor and the software the reader can be used for both routine and research applications. Standard errors of dark current and internal reference source over a three week period amount to 0.95% and 0.29% respectively. The lower detection limit for LiF2:Mg,Ti (TLD-700) is 10 µGy. The standard error of the peak position in forty irradiated CaF2:Dy (TLD-200) dosemeters corresponds to 0.5 oC.

An Aggregated Set of Integrated Fluidic Modules: Design Fundamentals

The paper is concerned with principles underlying the design of a set of integrated fluidic modules for local pneumatic control systems.The set can perform a long list of functions such as those of pulse counters, shift registers, logical modules, threshold elements, amplifiers, oscillators, phase and phase-frequency discriminators, and multipliers.Examples of using the set in actual hardware are given.