Analysis and design of low power wideband programmable frequency divider in 0.13-μm SiGe BiCMOS technology

Abstract

In this paper, a newly analytical method is proposed for the design of programmable frequency dividers. The more accurate transfer function of the current mode logic (CML) stage is used to analyze the injection-locking behavior models of the dual-modulus prescaler, and the general analytical expressions of the locking range of the prescaler are derived. Based on the analytical expressions that can be calculated using device-level circuit parameters obtained through DC and AC simulations, the dual-modulus prescaler design can be optimized quickly and accurately, thereby extending the frequency-division range of the programmable frequency divider. The proposed analytical method is verified by the measured results of the 2–22 GHz programmable divider, fabricated in 0.13-μm SiGe BiCMOS technology. By using heterojunction bipolar transistors (HBTs) in the dual-modulus prescaler and metal–oxidesemiconductor field-effect transistors (MOSFETs) in the pulse and swallow counters, the proposed programmable divider achieves the lowest power consumption of 63.3 mW and the best FOMT compared with previously works.