Pseudo-random Binary Sequence Generator Research Articles

Enhancing FPGA Testing Efficiency: A PRBS-Based Approach for DSP Slices and Multipliers

The multiplication operations are pivotal in (Application-Specific Integrated Circuits) ASICs and Digital Signal Processors (DSPs). The integration of Field-Programmable Gate Arrays (FPGAs) into modern embedded systems, efficient Built-in Self-Tests (BISTs), particularly for complex components like DSP slices, is essential. This paper evaluates Pseudo Random Binary Sequence (PRBS) generators and checkers as BIST tools for high-speed data transfers in FPGAs. The design achieves minimal errors and remarkable efficiency with less than 4% logic utilization within available Look-Up Tables (LUTs). The testing of embedded multipliers in modern FPGAs is analyzed, shedding light on their performance. The analysis includes Built-in Self-Test (BIST), PRBS generator, PRBS checker, and Bit Error Rate (BER), providing insights into FPGA-based testing. This analysis assesses PRBS tools for high-speed FPGA data transfers. A hybrid multiplier design, featuring BIST and PRBS capabilities, notably reduces DSP slice utilization from 16% to 5%. This liberated FPGA resource enhances operational capabilities. The runtime PRBS data control at the block level design exemplifies adaptability in FPGA testing. The findings underscore PRBS-based BIST potential in FPGA testing. The hybrid multiplier not only optimizes FPGA resources but also aligns with dynamic digital system requirements. This research aids FPGA designers and engineers in advanced testing strategies for evolving embedded systems.

64-GHz Operation of the Pseudorandom Binary Sequence Generator Using the Dual RSFQ/ERSFQ Standard Cell Library

A pseudo-random binary sequence of 7-bit word length (PRBS-7) generator has been designed as a low complexity circuit to validate the dual RSFQ/ERSFQ standard cell library, the circuit simulation methodology using process corners and Monte-Carlo statistical variations, as well as the digital design methodology using Verilog simulations with load-dependent timing back-annotation. The PRBS-7 design was optimized across multiple process corners with Monte-Carlo circuit simulations by incorporating statistical variations of the process parameters. To validate the digital design flow, the PRBS-7 was simulated using the Verilog behavioral descriptions of library cells. Using Liberty files for different global bias current (XI) process corners, the margins obtained from digital simulation were compared with circuit simulations. A 5 mm × 5 mm chip, incorporating both, the RSFQ and ERSFQ variant of the PRBS-7, was fabricated in the MIT-LL 100 μA/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SFQ5ee fab node. The RSFQ variant of the PRBS-7 has been successfully tested up to 64.77 GHz clock frequency, and the ERSFQ variant up to 45.72 GHz clock frequency. In addition, we have analyzed the model-to-hardware correlation for RSFQ PRBS-7 for different clock frequencies. The simulations account for two process parameters, critical current density ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_c</i> ) and sheet resistance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R_s</i> ).

Power Optimization of 50 GHz ERSFQ Circuits

The Energy-efficient Rapid Single Flux Quantum (ERSFQ) logic family offers zero-static power dissipation. Any ERSFQ circuit requires a feeding Josephson transmission line (FJTL), a relatively large active transmission line, which serves as an accurate voltage source. For proper operation, the FJTL needs to be continuously pumped at a frequency that is equal to or higher than the highest clock frequency of the ERSFQ circuit. We selected an on-chip pseudo-random binary sequence (PRBS) generator as the example circuit since it naturally facilitates quantitative measurements of operating bias margins in terms of bit error rate (BER). Using external and internal flux pump sources, we performed extensive experimental studies on BER for ERSFQ PRBS generators operating at clock frequencies up to 50 GHz. We paid special attention to the over-pumping regime, where the FJTL pump frequency is higher than the PRBS clock frequency and confirmed its superiority in improving BER. At 35.56 GHz clock frequency, a group of 4 PRBS generators and 4 individual FJTLs with the bias current ratio (BCR) equal to 1, had a BER lower than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> and bias margins of ±25% for internal and external flux pump sources over-pumping at 6.25% above clock frequency. The maximal operational clock frequency of a single ERSFQ PRBS generator with intrinsic pump source (+6.25% over-pumping) and BER <10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> was 49.53 GHz. We also focused on optimization of the FJTL's size to reduce the power consumption and the area occupied by the FJTL itself. All chips were fabricated at MIT-Lincoln Laboratory using the SFQ5ee fab node. Future steps required for better understanding of ERSFQ operation are discussed.

Demonstration and Comparison of On-Chip High-Frequency Test Methods for RSFQ Circuits

On-chip high-frequency test for Rapid Single Flux Quantum (RSFQ) circuits without external high-frequency equipment is very attractive and promising. The test method based on Shift Register (SR) is widely used for long time. Recently, we have proposed two test methods based on Pseudo Random Binary Sequence (PRBS) generator. In this paper, a Full Adder (FA) is taken as an example of circuit under test and the design methodology of the above approaches is presented. For FA with the traditional and two proposed approaches, the high-frequency test circuits are fabricated and tested. We demonstrate the successful measurement of the three circuits with the maximum operating frequency of the full adder at 23.3 GHz, 26.2 GHz and 27.4 GHz respectively. Based on the experimental results, the clock frequency measurement in the proposed two PRBS based test systems is more accurate and time-saving, which is advantageous for high-frequency RSFQ circuits measurement.

60-GHz Single Flux Quantum Pulse Transfer Circuit for Serial Biasing

Serial Biasing (SB) is a technique to reduce the total DC bias current of Rapid Single Flux Quantum (RSFQ) circuits by partitioning a design into several islands with isolated grounds and sequential biasing. In this paper we focus on the design of a driver-receiver pair (DRP) to transfer pulses between islands that are galvanically isolated for pulse streams. We discuss both DRP itself and the structure for its testing, that comprises several DRPs connected in series, on-chip pseudo random binary sequence (PRBS) generator for circuit stimulation, and HF output interface. We use the layout of DRPs’ chain as an example to illustrate the advantage of the grapevine (GV) approach, introduced earlier, to manage the bias current flowing into and out of an island. The GV current management technique is analyzed by both electromagnetic simulations and measurement, compared, and contrasted with the so-called ‘straightforward’ (SF) approach. The maximum operational frequency for SF test structure was 10 GHz with zero margins for the SB current. Measurements of the GV structure at 10 GHz demonstrated BER of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> with ±5.8% margins for SB current. We observed the correct operation of the 5-island DRP chain up to 60 GHz using the grapevine approach for SB current management. All chips were fabricated at MIT Lincoln Laboratory using SFQ5ee fab node.

Spread-Spectrum Modulated Multi-Channel Biosignal Acquisition Using a Shared Analog CMOS Front-End.

The key challenges in designing a multi-channel biosignal acquisition system for an ambulatory or invasive medical application with a high channel count are reducing the power consumption, area consumption and the outgoing wire count. This paper proposes a spread-spectrum modulated biosignal acquisition system using a shared amplifier and an analog-to-digital converter (ADC). We propose a design method to optimize a recording system for a given application based on the required SNR performance, number of inputs, and area. The proposed method is tested and validated on real pre-recorded atrial electrograms and achieves an average percentage root- mean-square difference (PRD) performance of 2.65% and 3.02% for sinus rhythm (SR) and atrial fibrillation (AF), respectively by using pseudo-random binary-sequence (PRBS) codes with a code-length of 511, for 16 inputs. We implement a 4-input spread-spectrum analog front-end in a 0.18 μm CMOS process to demonstrate the proposed approach. The analog front-end consists of a shared amplifier, a 2nd order Σ∆ ADC sampled at 7.8 MHz, used for digitization, and an on-chip 7-bit PRBS generator. It achieves a number-of-inputs to outgoing-wire ratio of 4:1 while consuming 23 μA/input including biasing from a 1.8 V power supply and 0.067 mm2 in area.

Encryption Using Optical Pseudo-Random Binary Sequence Based on Optical Logic Gate

In this paper, we propose a scheme for high-speed all-optical Pseudo-Random Binary Sequence (PRBS) generator and use it for generating keystream for encryption. This PRBS generator design is based on Linear Feedback Shift Registers (LFSR) and optical XOR and AND gates. The optical logical gates are based on quantum dot-semiconductor optical amplifier Mach-Zehnder interferometer (QD-SOA-MZI). With two photon absorption (TPA) in quantum dot-semiconductor optical amplifier (QD-SOA), this kind of optical logic gates performs well when processing data in an ultra-fast timescale and therefore able to function as high speed PRBS generator. Result shows that it’s possible for this scheme to realize all-optical encryption and decryption at high process rate up to 320 Gb/s. We simulated different ways of generating keystream with schemes such as cascaded generator, parallel generator and alternating step generator. These generators use more than one LFSR. Result shows that the schemes we use can function as stable and complex keystream generators.

Serial Biasing Technique for Electronic Design Automation in RSFQ Circuits

There has been renewed interest and efforts in increasing the complexity of superconductor circuits by means of electronic design automation (EDA). Serial biasing (SB) is a technique that reduces the total dc bias current required by large rapid single flux quantum (RSFQ) circuits, including its energy-efficient variant, ERSFQ. We believe SB needs to be incorporated in any EDA flow for large circuits. In SB, equally biased circuit blocks are placed on galvanically isolated islands and biased in series. SFQ pulses are transferred between islands by means of driver-receiver pairs (DRPs). The special current management technique, called the grapevine (GV) approach and introduced earlier, is used to handle the bias current flowing in and out of an island. In this article, we present all required layout primitives needed to implement SB for the IARPA-led SuperTools cell library that targets the SFQ5ee fab node at MIT Lincoln Laboratory. We discuss the horizontal and vertical composite driver-receiver pairs that comprise not only DRPs but also transmitters and receivers for passive transmission lines. We present the basic blocks to implement the GV managing technique for current injection and extraction. As a proof of concept, we designed a four-island test circuit that comprises all discussed layout primitives and employs an on-chip pseudorandom binary sequence generator as a test pattern source. The test circuit worked up to 50 GHz at the BER level of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> . We discuss future steps to improve the SB technique.

Impact of finite bandwidth on PRBS-modulated optical spectra.

Applying a pseudo-random binary sequence (PRBS) to phase modulators is a recent development in the broadening of optical spectra of laser sources to defeat stimulated Brillouin scattering (SBS). The theoretical underpinning of this method relies on alternating the phase of the optical signal between its native value and an out-of-phase value (i.e., imposing a binary phase shift of 0 or π in a pseudo random manner) to prevent coherent buildup of the SBS acoustic grating. In real physical systems, realizing such a binary shift is impossible due to the finite response times of the electronics and electro-optic components. The influence of these effects is investigated in this work, specifically the finite bandwidth of the electronic PRBS generator and the frequency-dependent response of the phase modulator, on the resultant temporal waveforms of the PRBS signal and its RF optical spectra. It is found that the optimal SBS suppression in real systems is achieved when the phase modulator is driven at a voltage beyond V π, even though driving at V π has been deemed as ideal. Moreover, both the SBS suppression and spectral broadening are always weaker than what is predicted by analytical results since any degradation of the sharp edges of the PRBS signal result in loss of high-frequency content in the RF spectrum of the PRBS signal. Lastly, it is noticed that the typical ways of measuring spectral width are not relevant when applied to the complex PRBS RF optical spectrum. An 'equivalent spectral width' is defined to accurately quantify the correlation between spectral width an SBS suppression.

Identification Approach for Nonlinear MIMO Dynamics of Closed-Loop Active Magnetic Bearing System

A systematic identification approach for the rotor/radial active magnetic bearing (rotor/RAMB) system is presented in this study. First, the system identification of the controller of commercial TMP is undertaken, and the corresponding linear dynamic models are constructed. To perfectly excite the nonlinearities of the rotor/RAMB system, a parallel amplitude-modulated pseudo-random binary sequence (PAPRBS) generator, which possesses the merits of no correlation among the perturbation signals, is employed. The dynamics of the rotor/RAMB system is identified with a Hammerstein–Wiener model. To reduce the difficulty of the identified two nonlinear blocks, the output nonlinear characteristics are estimated prior to the recursive process. Two conventional nonlinear model structures, i.e., NARX and NARMAX, are employed for comparison to verify the effectiveness of the identified Hammerstein–Wiener model. The averaged fit values of the Hammerstein–Wiener model, NARX model, and NARMAX model are 93.25%, 88.36%, and 76.91%, respectively.

Microring resonator-based all-optical parallel pseudo random binary sequence generator for rate multiplication.

In this paper, we design an all-optical Pseudo Random Binary Sequence (PRBS) generator in parallel configuration for operating rate multiplication purposes. The sequential circuit comprises of several clocked D flip-flops, XOR gates and multiplexers implemented using microring resonator (MRR)-based switches. The proposed design is demonstrated and validated through simulations for 500 Gb/s and 400 Gb/s rate doubling and quadrupling, respectively, of a 5-bit degree PRBS. The MRR critical operating parameters are also optimized against performance metrics through numerical investigation.

A full duplex FSO transmission system using RZ-4PAM downlink signals with 67% duty cycle and AMI uplink signals

To improve the transceiver quality of Free Space Optical (FSO) system and ensure that user access is feasible the network, a high-speed full-duplex 100 meters FSO transmission scheme using 67% duty cycle RZ-4PAM downlink and alternative mark inversion (AMI) uplink signals is designed system. In the downlink, one PAM sequence generator and one Mary pulse generator (MPG) module are used to generate 67% RZ-4PAM optical signals at 10Gbit/s through a Mach-Zehnder intensity modulator (MZM). The upstream AMI signals generator by the pseudo-random binary sequence (PRBS) generator and the precoding process. We have measured optical spectrums, time-domain waveforms and eye diagrams before and after signals transmission by system simulation. The transceiver performance of the downstream RZ-4PAM with 67% duty cycle and upstream AMI optical signals the in the 100m FSO transmission system is analyzed.

A Pseudo Random Binary Sequence Generator Based on Chaotic Logistic Maps

One of the major applications of Pseudo-Random Numbers is cryptography. Cryptography is a technique of securing information and communications through the use of codes so that only those people for whom the information is intended can understand it and process it thus preventing unauthorized access to information. Attackers can bypass cryptography, hack into computers that are responsible for data encryption and decryption, and exploit weak implementations, such as the use of default keys. To tackle this problem, logistic chaotic maps are used to generate a Pseudo-Random Binary Sequence (PRBS). The output of the designed PRBS Generator has successfully passed all the performance assessments of the NIST test suite. Hence a highly efficient Cryptographic Pseudo Random Bit Sequence Key is developed which not only has good performance in terms of statistical properties but can also achieve high product throughput if realized by FPGA hardware.

Proposal for ultrafast all-optical pseudo random binary sequence generator using microring resonator-based switches

An all-optical pseudo-random binary sequence (PRBS) generator is designed and simulated employing micro-ring resonators (MRRs) as the core technology. The PRBS generator consists of serially connected D flip-flops realized with double-bus MRR-based switches that exploit two-photon absorption induced in a pump-probe configuration, and of a MRR-based feedback XOR gate whose design is simpler than previously reported. The expected operation is theoretically validated for 3-bit and 4-bit degree PRBS generators and can be extended to higher PRBS orders with the straightforward addition of extra MRR-based D flip-flops. The MRR critical parameters, including radius, coupling coefficient and detuning, are optimized against performance metrics through numerical simulation at 250 Gb/s. The selection of these parameters according to the derived specifications can render feasible the practical implementation of the scheme and its exploitation for all-optical signal processing purposes.

A 15-Gb/s 0.0037-mm² 0.019-pJ/Bit Full-Rate Programmable Multi-Pattern Pseudo-Random Binary Sequence Generator

This brief presents a compact low-power programmable multi-pattern pseudo-random binary sequence (PRBS) generator. It is capable of producing 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> - 1, 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> - 1, 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">23</sup> - 1 and 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> - 1 test patterns to meet multiple testing requirements. To reduce power and area, the full-rate architecture with the truly-single-phase clock logic (TSPC) D-flip-flops (DFF) instead of the current-mode logic (CML) DFF is adopted. The multiplexer (MUX) merged TSPC DFF is proposed to avoid the delay of the MUX in conventional multiple pattern PRBS generators. Hence, the critical path delay is reduced, and thus, the maximum data rate can be improved. Fabricated in a 40-nm CMOS process (260-GHz <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> f_T</i> ), this PRBS occupies a core active area of 0.0037 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and operates at a maximum data rate of 15 Gb/s. The measured power consumption is 8.778 mW with 1.1-V supply. The figure-of-merit (FoM) is 0.019 pJ/bit at the pattern length of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> - 1.

Overfitting effect of artificial neural network based nonlinear equalizer: from mathematical origin to transmission evolution

Overfitting effect of artificial neural network (ANN) based nonlinear equalizer (NLE) leads to a trap of bit error ratio (BER) overestimation in optical fiber communication system, especially when the performance is evaluated by the commonly-used pseudo-random binary sequence (PRBS). First, we mathematically investigate the PRBS generation and Gray code mapping rules, in comparison with the use of Mersenne Twister random sequence (MTRS). Under the condition of a symbol erasure channel, we identify that ANN can recognize both the PRBS generation and symbol mapping rules, by increasing the weights of NLE at specific positions, whereas the MTRS is currently safe owing to the limited input length of current ANN based NLE. Then, we design four channel models of fiber optical transmission to experimentally examine various impairments on the evolution of overfitting effect. When both the additive white Gaussian noise (AWGN) channel and the bandwidth limited channel are considered, the mitigation of overfitting becomes possible by the use of pruned PRBS (P-PRBS) training set with removing the generation and mapping rules determined input symbols. However, as for both the chromatic dispersion (CD) uncompensated channel and the CD managed channel, the overfitting effect becomes serious, because both CD and fiber nonlinearity induced inter-symbol interference (ISI) is beneficial for ANN to identify the PRBS symbol rules. Finally, possible solutions to mitigate the overfitting effect are summarized.

A 1-pJ/bit 80-Gb/s $2^{15}-1$ PRBS Generator With a Modified Cherry–Hooper Output Driver

An 80-Gb/s $2^{15}-1$ pseudorandom binary sequence (PRBS) generator suitable for testing binary communication systems is presented. Implemented in a 130-nm SiGe process, the circuit is optimized for low power dissipation. For the core functionality, an energy efficiency of 1 pJ/bit is achieved, which is one of the best values among comparable published designs. In addition, the improvement of the output signal in time domain and frequency domain is targeted. The key factors affecting an ideal PRBS spectrum are identified and addressed from the system and circuit point of view. This results in spur suppression of higher than 40 dB, which is 15 dB better than previously reported works exceeding 40 Gb/s. As an output driver, a modified Cherry–Hooper amplifier is chosen. A parametrized design methodology for obtaining Bessel response is introduced and the amplifier is optimized for low power operation. Measurement results show a single-ended output signal with over 300-mV eye opening, 0.6-ps rms jitter, and a signal-to-noise ratio better than 10.5 at 80 Gb/s, which is the best-in-class output eye diagram for a PRBS generator, to the best of our knowledge.

Wideband Sparse Signal Acquisition Based on Serial Multi-Coset Sampling

Traditional parallel multi-coset sampling (MCS), which has several sub-Analog-to-Digital-Converters (sub-ADCs) working parallelly, is an attractive sub-Nyquist sampling technique for wideband sparse signals. However, the mismatch among sub-ADCs in traditional parallel MCS, such as bias, gain, and timing skew mismatch, degrades the signal acquisition performance greatly. In this paper, a serial MCS scheme based on clocking single ADC with nonuniform clock is proposed. The nonuniform sampling clock is generated by a pseudo-random binary sequence generator. An additional Sample/Hold (S/H) is used to improve the analog bandwidth of the serial MCS. Moreover, universal sampling pattern is designed for the proposed serial MCS. The sampling pattern design should not only maximize the Kruskal rank of compressed sensing matrix but also take the ADC’s sub-Nyquist sampling rate into consideration. Numeral experiments are presented demonstrating that the mismatch among sub-ADCs in traditional parallel MCS degrades the reconstruction performance greatly, and the proposed serial MCS can avoid the mismatch tactfully.

A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer

A digital-intensive on-chip serial link achieving a 10 Gb/s data rate over a 10-mm interconnect was demonstrated in a 65-nm GP process. A three-tap half-rate feed-forward equalizer was implemented for signal pre-emphasis in the transmitted block. On the receiver (RX) side, a two-tap half-rate time-based decision feedback equalizer was employed to cancel out inter-symbol interference noise. A 215 – 1 pseudorandom binary sequence generator and an in situ bit error rate (BER) monitor were designed for bit stream generation and convenient eye-diagram measurements. The measured energy efficiency of the transmitter and RX was 31.9 and 45.3 fJ/b/mm, respectively, for a data rate of 10 Gb/s. A BER less than 10−12 was verified for an eye width of 0.43 unit interval.

An Optical Duobinary Downlink Access Scheme Using Low Pass Filter and its Application

In this letter, a novel optical duobinary (ODB) downlink access scheme using low pass filter was proposed. The ODB downlink signal was generated by one continuous-wave (CW) laser, one pseudo-random binary sequence (PRBS) generator, one NRZ generator, one precoder, one Mach-Zehnder modulator and one low pass Bessel filter. The downlink signal can be transmitted over 20km singlemode fiber (SMF) and successfully received. We analyzed the time-domain waveforms, optical spectrum and eye diagrams before and after downstream transmission. The simulation results show that, compared to the traditional downlink scheme, this scheme has the advantages of high bandwidth efficiency, resistance to dispersion and good reception performance.