Proposed Frequency Synthesizer Research Articles

Анализ и разработка высокоточного генератора частоты w-диапазона с низким уровнем паразитных гармоник

For millimeter waves applications in the W-band 93.5-95.5 GHz, improved frequency synthesizers are highly demanded. Improved frequency synthesizer should be tunable synthesizer with high step resolution and possess high phase noise performance, low spurious harmonic levels and short locking time. These parameters are conflicting parameters in developing a high precision frequency oscillator with a pure spectrum. Therefore, it's necessary to make a compromisation between them. In this paper we present a frequency synthesizer based on a Gunn diode, two stable finely tuned frequency sources, a phase locked loop, and a 10th order subharmonic mixer in the feedback loop is built. The phase noise, spurious levels, and tuning step size of the phase locked loop generator are then analyzed, and the effect of each parameter on the others is introduced. To test the performance of the proposed frequency synthesizer using a spectrum analyzer, the output spectrum of the intermediate frequency was measured on a subharmonic mixer, which corresponds to the spectrum of a phase-locked loop generator. The results show that the proposed phase-locked loop generator can be tuned in steps of less than 1 Hz, and the first two spurious harmonics are far from the fundamental harmonic. These results can be used for designing an enhanced high precision frequency synthesizer with a low level of spurious harmonics and high phase noise performance in millimeter waves applications such as CW RADAR.

A 0.023–12 GHz ultra-wideband frequency synthesizer with FOMT of −251.8 dB

A fully integrated ultra-wideband fractional-N frequency synthesizer is presented in this paper. Ultra-wideband quadrature signals can be generated by an octave-wide fractional-N phase-locked loop (PLL) and an ultra-wideband local oscillator (LO) signal generator. An optimized dual-core voltage-controlled oscillator (VCO) is employed to maintain relatively constant loop parameters in the octave-wide operating range, while a negative-capacitance VCO (NC–VCO) is proposed to solve the frequency gap problem and enhance the design freedom of the wideband VCO. Moreover, a wide-range programmable multi-modulus divider (PMMD) with seamless switching and fractional division resolution is proposed for error-free division operation and quantization noise compensation in the fractional-N mode, respectively. Power-efficient design is mainly achieved by the presented hybrid LO generator with optimized divider topologies for different frequency ranges. Fabricated in a 55 nm CMOS process, 0.023–12 GHz continuous quadrature LO signals can be generated by the proposed frequency synthesizer which occupies an active area of 0.55 mm2 and consumes 75–104 mW from a 1.2 V supply. The measured phase noise is −108.1 dBc/Hz at 1 MHz offset from a 12 GHz carrier, and the I/Q phase error is less than 2.7° with FOMT of −251.8 dB.

Flexible Ultra-Wide Electro-Optic Frequency Combs for a High-Capacity Tunable 5G+ Millimeter-Wave Frequency Synthesizer

This paper presents a new scheme of a cost-effective tunable millimeter-wave (MMW) frequency synthesizer based on an ultra-wideband electro-optic frequency comb. The architecture for the quasi-tunable millimeter-wave frequency synthesizer mainly consists of a compact ultra-wide flat electro-optic frequency comb and a multi-tone frequency generator, which only includes a quantum dot mode-locked laser, a LiNbO3 dual-driving Mach–Zehnder modulator (DD-MZM) and Uni-traveling-carrier photodiode (UTC-PD). MMW signals generated with a quasi-tunable frequency are experimentally demonstrated. The difference in power is obtained for the different frequencies. The linewidth of the quasi-tunable frequency signals is less than 273 Hz. In addition, the single side band (SSB) phase noise of the 25, 37.5, 50 and 75 GHz is measured as −115, −106, −102 and −95 dBc/Hz at an offset of 1 kHz, respectively. The proposed frequency synthesizer has ultra-low phase noise, quasi-tunable frequency and simple structure. The research results of the frequency synthesizer are applied for 5G+ transmission with radio wave working at K-band and V-band. The flexible, compact and robust MMW frequency synthesizer is suitable for the future of ultra-high capacity 5G+ communication.

A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Bandwidth Control

This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.

A 5-GHz Adjustable Loop Bandwidth Frequency Synthesizer With an On-Chip Loop Filter Array

The design of an adjustable loop bandwidth (LBW) frequency synthesizer with an on-chip loop filter (LF) array is presented. The LF array based on the simple capacitor multiplier topology is proposed to support LBW switching between 500 kHz and 1 MHz while saving 82.9% chip size compared to the traditional LF array. The maximum capacitance of 108 pF is realized by using the capacitor multiplier with an on-chip capacitance of 6 pF. The proposed frequency synthesizer is implemented in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm CMOS process and supplied at 1.8 V with a current dissipation of 11.8 mA.

A 23–36.8-GHz Low-Noise Frequency Synthesizer With a Fundamental Colpitts VCO Array in SiGe BiCMOS for 5G Applications

This article describes a wideband low-noise frequency synthesizer implemented in 0.13- $\mu \text{m}$ SiGe BiCMOS process for 5G millimeter-wave applications. To extend the frequency range while reducing the phase noise, a fundamental voltage-controlled oscillator (VCO) array including four Colpitts VCO cores with switchable bias circuits is adopted in the proposed frequency synthesizer. A ring-oscillator-based injection locked frequency divider is utilized as the wideband divide-by-2 prescaler, and its bandwidth is optimized based on a new injection-locked behavior model. This fabricated frequency synthesizer can be locked in a range from 23 to 36.8 GHz (46.2%) by a 100-MHz step. It achieves a phase noise of −94.7 dBc/Hz at the 1-MHz offset and an output power of −3.5 dBm measured at 36.8 GHz. The chip consumes 360.6 mW from 3.3 and 1.8 V supplies and has an area of $2.7\times3.1$ mm2.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

Ultralow Phase Noise Optoelectronic Oscillator and Its Application to a Frequency Synthesizer

We propose a novel injection-locked OptoElectronic Oscillator (OEO) with ultralow phase noise based on two cascaded phase modulators, which is further applied to construct a frequency synthesizer. Thanks to the phase modulation, the output optical spectrum expands and the optical power keeps constant while passing through the optical fiber, which dramatically reduces the intensity noise induced by the nonlinear effects of the optical fiber. A dual-output MZI together with a balanced optical detector realizes the phase modulation to intensity modulation conversion and improves the signal to noise ratio of the OEO. The output frequency of the proposed OEO is 9.9999914 GHz with its sidemode suppression ratio larger than 85 dB, and the phase noise reaches –153.1 dBc/Hz at 10 kHz frequency offset which is 38.7 dB lower than that of Keysight E8257D. Moreover, a broadband, high performance frequency synthesizer is established based on the proposed OEO. Combining the DDS and PLL technologies, the proposed frequency synthesizer can cover 5.9～12.9 GHz range. The phase noise is around –130 dBc/Hz@10 kHz, the spur suppression ratio is better than 65 dB, and the frequency hopping time is less than 1.48 μs.

Design of 0.35-ps RMS Jitter 4.4–5.6-GHz Frequency Synthesizer with Adaptive Frequency Calibration Using 55-nm CMOS Technology

This paper demonstrates the design and implementation of a 5-GHz frequency synthesizer using 55-nm complementary metal-oxide semiconductor technology. The proposed synthesizer achieves an ultra-low 0.35-ps jitter with a high-resolution adaptive frequency calibration scheme that automatically chooses frequency-tuning curves and improves calibration accuracy. The proposed synthesizer employs a high-Q LC voltage-controlled oscillator, constant bandwidth, low, and even $$K_{\mathrm{VCO}}$$ technique using thermometer-weighted capacitor calibration, a low-power divider, and a charge-pump (CP) circuit to achieve low jitter. The oscillator comprises a modified digitally controlled capacitor and varactor array, which extend the tuning range and minimize the phase noise. A matched differential CP is adopted to reduce reference spurs and phase-noise performance. The proposed frequency synthesizer achieves an output frequency of 4.4–5.6 GHz with a chip area of $$0.33\hbox { mm}^{2}$$ . The power consumption is 20 mW from a 1.2-V supply at 5 GHz, and the reference spur is −67.99 dBc. The measured root mean-square random jitter and phase noise are 0.35 ps and −110.04 dBc/Hz at 1 MHz, respectively.

A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC

Generation of low jitter, high frequency clock from a low frequency reference clock using classical analog phaselocked loops (PLLs) requires large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. Specifically, their deterministic jitter (DJ), which is proportional to the loop update rate becomes prohibitively large at low reference clock frequencies. We propose a scrambling TDC (STDC) to improve DJ performance and a cascaded architecture with digital multiplying delay locked loop as the first stage and hybrid analog/digital PLL as the second stage to achieve low random jitter in a power efficient manner. Fabricated in a 90 nm CMOS process, the prototype frequency synthesizer consumes 4.76 mW power from a 1.0 V supply and generates 160 MHz and 2.56 GHz output clocks from a 1.25 MHz crystal reference frequency. The long-term absolute jitter of the 160 MHz digital MDLL and 2.56 GHz digital PLL outputs are 2.4 psrms and 4.18 psrms, while the peak-to-peak jitter are 22.1 ps and 35.2 ps, respectively. The proposed frequency synthesizer occupies an active die area of 0.16mm2 and achieves power efficiency of 1.86 mW/GHz.

A fractional-N frequency synthesizer for wireless sensor network nodes

This paper presents a fractional-N frequency synthesizer for wireless sensor network (WSN) nodes. The proposed frequency synthesizer adopts a phase locked loop (PLL) based structure, which employs an LC voltage-controlled oscillator (VCO) with small VCO gain (KVCO) and frequency step (fstep) variations, a charge pump (CP) with current changing in proportion with the division ratio and a 20-bit ΔΣ modulator, etc. To realize constant KVCO and fstep, a novel capacitor sub-bands grouping method is proposed. The VCO sub-groups' sizes are arranged according to the maximal allowed KVCO variation of the system. Besides, a current mode logic divide-by-2 circuit with inside-loop buffers ensures the synthesizer generates I/Q quadrature signals robustly. This synthesizer is implemented in a 0.13 μm CMOS process. Measurement results show that the frequency synthesizer has a frequency span from 2.07 to 3.11 GHz and the typical phase noise is −86.34 dBc/Hz at 100 kHz offset and −114.17 dBc/Hz at 1 MHz offset with a loop bandwidth of about 200 kHz, which meet the WSN nodes' requirements.

The 1‐V 2.4 GHz low‐spur fractional‐N frequency synthesizer chip design with exploiting randomly selected PFD and sub‐sampling charge pump technology

ABSTRACTA 1‐V 2.4 GHz low‐spur phase‐locked loop (PLL) fractional‐N frequency synthesizer with a subsampling charge pump and a randomly selected phase frequency detector is implemented by TSMC 0.18‐μm CMOS process. The proposed frequency synthesizer randomizes the periodic ripples on the controlled voltage from the voltage‐controlled oscillator to reduce the reference spur at the output of the PLL. A random clock generator is used to perform this random selection control. At 1‐V supply voltage, measured results of the proposed prototype achieve the tuning range of 2.235–2.579 GHz, corresponding to 14.3%, a phase noise of −113.17 dBc/Hz at 1 MHz offset frequency from 2.41 GHz, an output power of −4.534 dBm with a reference spur of −70.4 dBc and a power consumption of 9 mW. Including pads, the chip area only occupies 0.695 (0.819 × 0.849) mm2. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:61–66, 2015

Low noise frequency synthesizer with self-calibrated voltage controlled oscillator and accurate AFC algorithm

A low noise phase locked loop (PLL) frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75–11.5 GHz high frequency wide band local oscillator (LO) carriers. Tested 11.5 GHz LO bears a phase noise of−104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm2, including bias circuits and buffers.

A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX

This paper presents a low power and low phase noise CMOS integer-N frequency synthesizer based on the charge-pump Phase Locked Loop (PLL) topology. The frequency synthesizer can be used for IEEE 802.16 unlicensed band of WiMAX (World Interoperability for Microwave Access). The operation frequency of the proposed design is ranged from 5.13 to 5.22GHz. The proposed Voltage-Controlled Oscillator (VCO) achieves low power consumption and low phase noise. The high speed divider is implemented by an optimal extended true single phase clock (E-TSPC) prescaler. It can achieve higher operating frequency and lower power consumption. A new frequency divider is also proposed to eliminate the hardware overhead of the S counter in the conventional programmable divider. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump, a low-pass loop filter, a VCO, and a frequency divider. The simulated phase noise of the proposed VCO is −121.6dBc/Hz at 1MHz offset from the carrier frequency. The proposed frequency synthesizer consumes 13.1mW. The chip with an area of 1.048×1.076mm2 is fabricated in a TSMC 0.18μm CMOS 1P6M technology process.

A wide range sigma—delta fractional-N frequency synthesizer with adaptive frequency calibration

A wide range fractional-N frequency synthesizer in 0.18 μm RF CMOS technology is implemented. A switched-capacitors bank LC-tank VCO and an adaptive frequency calibration technique are used to expand the frequency range. A 16-bit third-order sigma—delta modulator with dither is used to randomize the fractional spur. The active area is 0.6 mm2. The experimental results show the proposed frequency synthesizer consumes 4.3 mA from a single 1.8 V supply voltage except for buffers. The frequency range is 1.44–2.11 GHz and the frequency resolution is less than 0.4 kHz. The phase noise is −94 dBc/Hz @ 100 kHz and −121 dBc/Hz @ 1 MHz at the output of the prescaler with a loop bandwidth of approximately 120 kHz. The performance meets the requirements for the multi-band and multi-mode transceiver applications.

디스플레이 인터페이스에 적용된 6 Gbps급 송신기용 PLL(Phase Locked Loop) 설계

최근 주파수 합성기는 협대역으로 설계를 하거나 광대역 주파수 합성기의 경우 이중루프구조로 설계하여 위상잡음을 줄이는 방식을 사용하고 있다. 그러나 이중루프구조의 주파수 합성기는 전압제어발진기의 중심주파수 불일치와 추가적인 루프를 필요로 하는 단점을 가지고 있다. 본 논문에서는 800Mhz ~ 3Ghz를 지원하는 새로운 구조의 단일루프 형태의 다중제어 광대역 주파수 합성기를 제안한다. 본 논문의 주파수 합성기의 전압제어발진기는 Coarse 제어 전압과 Fine제어전압을 고정되며, 최종적으로 낮은 Kvco를 가지게 된다. 주파수 합성기의 모의실험은 UMC <TEX>$0.11{\mu}m$</TEX> 공정에서 검증하였으며, 제안된 주파수 합성기는 다양한 응용분야에 사용될 수 있을 것으로 기대된다. Recently, frequency synthesizers are being designed in two ways narrow-band loop or dual-loop for wide-band to reduce the phase noise. However, dual-loop has the disadvantage of center frequency mismatch and requiring an extra loop. In this paper, we propose a new structure that supports a range of 800Mhz ~ 3Ghz with multiple control of the single-loop frequency synthesizer without another loop. The control voltage of the VCO(coarse, fine) will be fixed, and finally the VCO will have a low Kvco. The frequency synthesizer is simulated using UMC <TEX>$0.11{\mu}m$</TEX> process, proposed frequency synthesizer can be used in a variety of applications in the future.

Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD

This brief presents a low-spur phase-locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator to reduce the reference spur at the output of the PLL. A novel random clock generator is presented to perform the random selection of the phase frequency detector control for the charge pump in locked state. The proposed frequency synthesizer was fabricated in a TSMC 0.18-μm CMOS process. The proposed PLL achieved phase noise of -93 dBc/Hz with a 600-kHz offset frequency and reference spurs below -72 dBc.

Chip design of a 5.8-GHz fractional-N frequency synthesizer with a tunable Gm−C loop filter

This paper proposes a novel Gm−C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta (ΣΔ) modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is −114.1 dBc/Hz with lower Gm−C bandwidth and −111.7 dBm/C with higher Gm−C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and built-in Gm−C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is −8.69 dBm at 5.68 GHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage.

System-on-Package MHMIC Milimeter-Wave Frequency Synthesizer for 60 GHz WPANs

We present a low-cost millimeter-wave frequency synthesizer with ultralow phase noise, implemented using system-on-package (SoP) techniques for high-data-rate wireless personal area network (WPAN) systems operating in the unlicensed 60 GHz ISM band (57–64 GHz). The phase noise specification of the proposed frequency synthesizer is derived for a worst case scenario of an 802.11.3c system, which uses a 64-QAM 512-carrier-OFDM modulation, and a data rate of 5.775 Gbps. Our design approach adopts commercial-of-the-shelf (COTS) components integrated in a low-cost alumina-based miniature hybrid microwave integrated circuit (MHMIC) package. The proposed design approach reduces not only the system cost and time-to-market, but also enhances the system performance in comparison with system-on-chip (SoC) designs. The synthesizer has measured phase noise of -111.5 dBc/Hz at 1 MHz offset and integrated phase noise of 2.8° (simulated: 2.5°) measured at 57.6 GHz with output power of +1 dBm.

An All-Digital Large-$N$ Audio Frequency Synthesizer for HDMI Applications

In this brief, a novel all-digital and large-frequency-multiplication-ratio audio frequency synthesizer for high-definition multimedia interface applications is presented. The proposed large- N frequency synthesizer is designed in an all-digital manner to reduce circuit complexity and design efforts in advanced CMOS process technology, as compared with prior studies. The proposed frequency synthesizer does not require an extra high-frequency reference clock source but employs a single locking loop to reduce lock-in time and enhance loop stability. Based on the proposed frequency search algorithm and the high-resolution digitally controlled oscillator, the frequency synthesizer cannot only provide a large frequency multiplication ratio, but it also achieves low-jitter performance. Measurement results show that the frequency multiplication ratio has a range of 4096 to 25 088 and that the power consumption of the proposed frequency synthesizer can be improved to 591 μW (at 24.576 MHz) with a peak-to-peak jitter of 1.23%. In addition, the proposed frequency synthesizer can be implemented with standard cells, making it easily portable to different processes and very suitable for system-on-a-chip applications.