Propagation Delay Time Research Articles

A time-delay COVID-19 propagation model considering supply chain transmission and hierarchical quarantine rate

In this manuscript, we investigate a novel Susceptible–Exposed–Infected–Quarantined–Recovered (SEIQR) COVID-19 propagation model with two delays, and we also consider supply chain transmission and hierarchical quarantine rate in this model. Firstly, we analyze the existence of an equilibrium, including a virus-free equilibrium and a virus-existence equilibrium. Then local stability and the occurrence of Hopf bifurcation have been researched by thinking of time delay as the bifurcation parameter. Besides, we calculate direction and stability of the Hopf bifurcation. Finally, we carry out some numerical simulations to prove the validity of theoretical results.

Medium Access Control Under Space-Time Coupling in Underwater Acoustic Networks

The long propagation delay presents a nonnegligible impact on medium access control (MAC) in underwater acoustic networks (UANs), leading to the coupling of spatial propagation delay and transmission time in determining frame collisions at receivers. To this end, this article first reveals the space-time coupling relationship for collision-free transmissions. We find that the interference region for simultaneous transmissions is an annulus, which is much smaller than the whole transmission range. Thus, UANs have more spatial multiplexing opportunities than terrestrial radio networks. By deriving the collision probabilities of the ALOHA-based protocols, we show that the annulus interference region in UANs provides potential to improve random access protocols. We further derive the heuristics for optimal scheduling for periodical transmissions under space-time coupling, which is formulated as a mixed-integer linear programming problem. The obtained heuristics are then used to design low-complexity algorithms, which are verified by simulation results. Our proposed algorithms can achieve the optimal scheduling in star networks and outperform the existing MAC in mesh networks.

Statistical Strategies to Capture Correlation Between Overshooting Effect and Propagation Delay Time in Nano-CMOS Inverters

In this paper, we model statistical correlation between overshooting effect and propagation delay time in nano-CMOS technology considering the influence of intrinsic parameter fluctuations caused by discreteness of charge and granularity of matter. The impact of input slew rate, output capacitive load, and supply voltage on this statistical correlation is comprehensively studied. Moreover, we propose two alternative approaches which are capable of reproducing the statistical correlation as well as mean and standard deviation of both propagation delay time and overshoot voltage. We evaluate the accuracy of these alternative approaches against accurate Monte-Carlo simulations. It is shown that the statistical correlations are almost preserved using these alternative approaches.

2Pb5-1 Investigation on improvement of spatial resolution of ultrasound images by considering propagation delay time of transmitted wave

2Pb5-1 Investigation on improvement of spatial resolution of ultrasound images by considering propagation delay time of transmitted wave

A time-delay propagation model for studying illegal crossing behavior of E-bikes on a regular lattice

Violation behavior of e-bikes at the signal intersection is usually induced by the ‘herd effect’, which may easily lead to dangerous accidents. In order to study the propagation mechanism of e-bikes’ illegal crossing, taking the high mobility and flexibility of e-bikes into account, this paper proposes an illegal time-delay model based on the theory of regular Lattice. A typical signal intersection of Guilin was selected as the study subject. Its topological features are analyzed through field survey and video shooting. Further, how the violation behavior of e-bikes with different structural features evolves was investigated. Results show that the herd illegal behavior of e-bikes is sensitively affected by the degree, transmission rate, arrival rate and crossing time. Specifically, a slight increase of any of the above factors will dramatically boost the violation behavior across the whole intersection. This study may give insight into why the illegal crossing of e-bikes prevails, and help to facilitate intersection design and signal control in the future.

A Simple Desaturation-Based Protection Circuit for GaN HEMT With Ultrafast Response

Similar to other power semiconductors, gallium nitride enhancement-mode high-electron-mobility transistors (GaN E-HEMTs) require short-circuit protection (SCP) or overcurrent protection (OCP) in practical applications. However, the fast-switching characteristic of GaN introduces the challenge to the protection. For SCP, the traditional methods are either too slow or not practical for GaN. Therefore, an alternative SCP solution, which is fast and easy to implement, is much desired. For high power density applications, it is also popular to integrate OCP into the gate driver. Therefore, a fast protection circuit that can be used for either SCP or OCP is desirable. In this article, an ultrafast discrete circuit-based protection circuit is proposed for GaN HEMTs. It includes a first soft turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> stage and a second hard turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> stage. The soft turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> stage effectively limits the voltage spike over the device. Following the soft turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> stage, the hard turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> stage will cut off the pulsewidth modulation signal immediately completely. A dual-gate implementation approach is further proposed for devices with two gate pads. The method has been verified by both SPICE simulation and hardware implementations for both SCP and OCP. The experimental results show that the total propagation delay time for SCP is only 125 ns while the normal switching performance is not affected.

Thin Film Sequential Circuits: Flip-Flops and a Counter Based on p-SnO and n-InGaZnO

Oxide semiconductors have emerged as ideal candidate materials for flexible electronics and circuits. However, complementary flip-flops, which are the essential building blocks in sequential circuits, based on all-oxide thin-film transistors (TFTs) have not yet been demonstrated. Here, we employed n-type indium gallium zinc oxide and p-type tin monoxide to achieve J-K flip-flop (JK-FF) and D-type edge-triggered FF (D-FF). The operation properties of the JK-FF and D-FF were characterised both statically and dynamically. The output signals of the D-FF show great robustness. The D-FF shows very short propagation delay times of 17 and 40 μs from “0” to “1” and from “1” to “0”, respectively. Based on the D-FFs, a two-bit counter with 90 transistors was designed and fabricated successfully, acting as either up-counter or down-counter. To the best of our knowledge, this counter has the highest integration among the reported thin-film complementary sequential circuits based on all-oxide transistors to date.

Competing Failure Modeling for Performance Analysis of Automated Manufacturing Systems With Serial Structures and Imperfect Quality Inspection

Fierce global competition drives automated manufacturing systems (AMSs) to be increasingly complex, which poses significant challenges on performance analysis and production control. The multistage production via serial stations will lead to the propagation of failures in AMSs, which will affect system performance by triggering complex competitions among multiple failure modes. Although machine performance and product quality have been considered, very little has been done to investigate the effect of imperfect quality inspection on competing failures. Focusing on a time balance serial AMS, this article presents a new competing failure model to investigate the complex interactions among machine failures, product quality, and inspection process, which enables the characterizations of time-delayed propagation of failure, accumulation of degradation, and dynamics of states in serial AMSs. In order to further analyze the impact of competing behaviors on system performance, we have also developed decision diagram models and algorithms, which are evaluated and validated on serial AMSs with imperfect inspection, revealing the characteristic of multistate interactions. Experimental results show that the proposed methods have strong potentials for performance modeling and analysis of serial AMSs and also demonstrate general applicability for manufacturing decision making.

PDP and TPD Flexible MCML and MTCML Ultralow-Power and High-Speed Structures for Wireless and Wireline Applications

This article presents two novel structures for designing current mode logic (CML) digital circuits [MOS CML (MCML) and multiple tail CML (MTCML)] in ultralow-power (ULP) and high-speed (HS) applications. The transistor’s bulk can be used as a digital signal input at a level, where it does not cause a disturbance to the operation of the transistor. Therefore, the number of transistors used in novel structures is reduced and it is possible to improve power delay product (PDP) and time propagation delay (TPD) in some of the tail currents. This technique is obtained through integrating the bulk-driven technique into the CML digital circuits, which are in the form of bulk-driven MCML (BD-MCML) and BD-MTCML. In the conventional CMOS technology, the proposed structures depend on the type of substrate. The BD-MCML structure uses a deep n-well technology and the BD-MTCML uses an n-well technology. The CML gates, such as AND, XOR, and D-latch, are suggested. The systematic use of the proposed structures is discussed in both HS and ULP applications. Finally, an unsigned multiplier is designed in the form of the BD-MTCML with a conventional 180-nm technology. Mixed-signal circuits are Serial/De-serial (SerDes), optical receivers, radio frequency (RF) receivers, and line drivers on the HS approach, and also video processors and A/D and D/A converters on the ULP approach.

Printed Logic Gates Based on Enhancement- and Depletion-Mode Electrolyte-Gated Transistors

Electrolyte-gated thin-film transistors (EGTs) with indium oxide channel, and expected lifetime of three months, enable low-voltage operation (~1 V) in the field of printed electronics (PEs). The channel width of our printed EGTs is varied between 200 and 1000 μm, whereas a channel length between 10 and 100 μm is used. Due to the lack of uniform performance p-type metal oxide semiconductors, n-type EGTs and passive elements are used to design circuits. For logic gates, transistor-resistor logic has been employed so far, but depletion and enhancement-mode EGTs in a transistor-transistor logic boost the circuit performance in terms of delay and signal swing. In this article, the threshold voltage of the EGT, which determines the operation mode, is tuned through sizing of the EGTs channel geometry. The feasibility of both transistor operation modes is demonstrated for logic gates and ring oscillators. An inverter operating at a supply voltage of 1 V shows a maximum gain of 9.6 and a propagation delay time of 0.7 ms, which represents an improvement of ~ 2x for the gain and oscillation frequency, in comparison with the resistor-transistor logic design. Moreover, the power consumption is reduced by 6x.

A Timing Model for the Optimal Design of a Prototype Active-Matrix Display

Describing the dependence of both signal propagation delay and pixel charging time on display specifications and device parameters, a timing model and a combined coordinate system for its convenient visualization are developed for an active-matrix display. Presented also is an algorithm developed to optimally determine the width of the interconnects and that of the address transistor for maximizing the aperture ratio of a pixel. The model could be applied to search for optimal viable designs under different panel specifications and technology constraints.

Experimental investigation of pressure fluctuation propagation in two orthogonal directions using a clapboard-type internally circulating fluidized bed

In this work, the pressure wave propagation in the vertical and horizontal directions has been studied using a self-designed clapboard-type internally circulating fluidized bed. The effects of flow regimes and solid mixture on the pressure wave propagation characteristics were analyzed in terms of time-averaged pressure, standard deviation, power spectral density, dominant frequency, propagation time delay, and attenuation. The superficial velocity ratio had a remarkable effect on the pressure wave propagation time delay in the vertical direction but had less influence on the pressure wave propagation in the horizontal direction. The particle circulation provided an extra resistance force to the horizontal pressure wave propagation and resulted in an increase in the pressure wave decay factor in the horizontal direction. The addition of glass beads and salt greatly increased the time delay and decay factor both in vertical and horizontal directions. The addition of 15% corn powder (Geldart-C group) reduced the propagation time delay but increased the decay factor.

An observer deployment algorithm for information source positioning based on Naive Bayes

The accurate positioning of the propagation and diffusion source points of personal information is of great practical significance for the protection of personal information security. Currently, a popular method is to locate the data diffusion source point by deploying a certain number of observers and collecting the data propagation information from observers. In view of the deployment of observers, it was found that there is an important correlation between the observer deployment location and the data propagation time delay by analyzing the relationship between the positioning accuracy of information sources and the deployment location of observers, and then an optimal deployment strategy based on Naive Bayes model (NBM) was proposed. At last, it was verified that the proposed deployment strategy can significantly improve the positioning accuracy of information source by comparing the model network with the actual network, which is of great significance for the security control of personal information propagation.

Study On Early Warning Systems (EWS) for Indonesia Digital Terrestrial Television

Early warning system (EWS) via digital television (TV) in Indonesia is still un-optimal in design and implementation due to the absent of clear standard/guidance to follow across the country. This paper studies various EWS based on digital TV of Japan, Korea, and the United States of America (USA). Although the systems look like different, the EWS can be simplified into 3 nodes representing (i) Emergency Agency, (ii) TV broadcaster, and (iii) TV receiver. Beside the 3-node-based EWS, this paper evaluates the possibilities of EWS having 4 nodes. We perform computer simulations to evaluate the latency and bit error rate (BER) performances under additive white Gaussian noise (AWGN) and frequency-flat Rayleigh fading channels. We found that the system latency and BER performances of EWS are highly affected by (i) the distance of one node to another and (ii) the number of nodes, where EWS with 3 or 4 nodes found to be enough and suitable for Indonesia digital TV. We propose a criterion of good EWS, i.e., total delay T &lt;= t + 4.delta.t with t and delta.t being the propagation delay and processing time, respectively, and BER less than Pb=10-3. The result of this paper are expected to be used as a reference for the Indonesia EWS systems.

Design and simulation of high-performance 2:1 multiplexer based on side-contacted FED

Designing a high-quality switch block ensures the efficient data transmission in digital circuits and systems. In this paper, an innovative 2:1 multiplexer is successfully designed based on the previously proposed side-contacted field-effect diodes (S-FEDs) at 180 nm SOI technology node. Optimization of the reservoir thickness and gate work function of the S-FED satisfy high ION/IOFF ratio and noise-immunity. DC, AC, and transient mixed-mode simulations are employed to scrutinize and compare performance of constituent logic gates based on the S-FED and CMOS. Simulation results demonstrate superior noise margins up to 100 mV for the S-FED-based inverter compared with the CMOS-based counterpart. Furthermore, the S-FED-based transmission gate with switching frequency of 38.9 GHz can act as a high-speed alternative for the CMOS-based one. Both multiplexer architectures configured by the S-FED and CMOS are compared in terms of performance parameters. In this regard, average power consumption and PDP quantities for the S-FED-based multiplexer reveal significant reductions by about 2 and 3 orders of magnitude, respectively, compared with the CMOS-based one. In addition, propagation delay time increases drastically with scaling power supply in the CMOS-based multiplexer; while, this increase is suppressed for the S-FED-based version.

Ultrasound Powered Implants: Design, Performance Considerations and Simulation Results

Ultrasounds (US) has been used in the past decades as a non-invasive imaging modality. Although employed extensively in clinical applications for soft tissue imaging, the acoustic beams can also be used for sensing and actuation for biological implants. In this paper we present a unified three dimensional (3D) computational framework to simulate the performance and response of deeply implanted devices to US stimulation and composed by a double piezoelectric layer with different material composition and configurations. The model combines the temporally-invariant distribution of the scattered pressure field arising from the presence of scatterers and attenuators in the domain of simulation, with the time-delay propagation of waves caused by refraction, to solve the Forward Problem in US within the breast and lower abdominal regions. It was found that a lens-shaped implant produces higher peak echoes in the breast for frequencies ≤ 6 MHz whereas, in the liver, similar strengths are obtained for the lens and disk-shaped implants in the higher spectrum. Regarding material composition, a combination of LiNbO3 with PZT-5A yielded higher amplitude signals, when the double layer thickness is comparable to the wavelength of excitation. Experimental validation of the proposed model was carried out in the presence of a synthetic anatomical phantom of the breast and water tank to investigate the acoustic signals generated by disk-shaped implants when stimulated by external US sources in the harmonic and impulsive regimes of wave propagation. The implantation of a double piezoelectric layer inside the human body can, in the future, provide a high resolution system for the detection of surgical site infection as well as tumour growth and other systemic inflammatory responses originating deeply in soft tissues.

Runtime Verification of Business Cloud Workflow Temporal Conformance

Business cloud workflows are often designed with multiple time constraints for timely response to business requests. To ensure on-time completion of workflow instances, workflow temporal conformance state needs to be constantly monitored and verified at runtime. Considering the fact that there are a large number of workflow instances running in a parallel fashion in many business scenarios, conventional verification approaches for time-related properties using such as temporal logic or timed Petri nets are not feasible due to the limitation of low efficiency at runtime. To address this issue, we propose a new approach to automated runtime verification of temporal conformance for parallel workflow instances in a cloud environment. Instead of using response time to verify temporal conformance of every single workflow as in conventional strategies, workflow throughput is employed as the performance measurement to efficiently monitor a large number of parallel workflow instances. On this basis we present a novel conformance verification strategy. This strategy considers the effect of time delay propagation in the cloud workflow systems to accurately verify workflow runtime temporal conformance. Our verification strategy is implemented in a prototype cloud workflow system and the evaluation results show that it outperforms the state-of-the-art workflow temporal verification strategy.

A Radix-16 Booth Multiplier Based on Recoding Adder with Ultra High Power Efficiency and Reduced Complexity for Neuroimaging

In the current medical developments the neuro imaging plays a vital role in the study of a human brain related disorders. The accuracy of the brain study is mainly dependent on the images created from the scanners at a rapid speed. In achieving this we need a high speed and low power consuming scanners. The current scenario in VLSI design, the scanners highly rely on a high speed Digital Signal Processor (DSP), which generally depends on the speed of a multiplier. Multipliers are considered as a more complex component when compared with adders. The current techniques provide greater access to high-speed multipliers which are designed with less area that consume low power. The major constraints to be considered for an efficient multiplier design are propagation time delay and power dissipation, especially during the ideal time. An approximate recoding adder is proposed to reduce the existing booth multiplier's immensity. It increases the accuracy and reduces complexity through this technique; however, it has an issue with Power Delay Product (PDP) and power dissipation. To solve this problem, the proposed system is designed with a power gating based 16 × 16 bit Booth multiplier based on approximate recoding adder. It decreases the power dissipation and minimizes the length and width of the partial products for speeding up the multiplication process. The results obtained from the simulation show that the designed power gating based Radix multiplier circuits achieves better PDP, average power and area. The achieved results are compared with a Radix based multiplier, power gating CLA based multiplier and CLA based multiplier.

Reflected BSDEs with time-delayed generators and nonlinear resistance

We consider a time-delayed backward stochastic differential equation constrained above a given continuous barrier and having an additional resistance term in the generator. Existence and uniqueness results are provided on a small time horizon. We also provide a stability result with respect to the delay measure.

Effect of manufacturing technics on the microstructure and temperature-affected electrical performance of D-type latch devices

In this study, the D-type latch devices with Ceramic Flat Package (CFP) and Shrink Small-Outline Package (SSOP) were tested and analyzed by experimental means. The effects of manufacturing technics on the pin structure, wire bond, chip layout design, die attach and temperature-affected electrical performance were subsequently investigated. Results show that manufacturing technics with CFP package possesses thicker special pin coatings, thicker different wire bond, stable and effective die attach compared with SSOP package. Meanwhile, the bare dies of two devices exhibit same layout structure design but different longitudinal dimensions. The temperature-affected electrical performances including voltage, current and propagation delay time reveal that the temperature sensitive parameters of CFP latch (variation about 1%) display 12 times better stability than that of SSOP latch (distinct variation about 12%) from −55 ​°C to 125 ​°C. Meanwhile, the SSOP latch displays 41.8% better switching speed and working frequency than CFP latch with similar other electrical parameters at room temperature.