Stored Program Research Articles

Demonstration of a novel majority logic in a memristive crossbar array for in-memory parallel computing.

A memristive crossbar array can execute Boolean logic operations directly within the memory, which is highly noteworthy as it addresses the data bottleneck issue in traditional von Neumann computing. Although its potential has been widely demonstrated, achieving practical levels of operational reliability and computational efficiency remains a challenge. Here, we introduce a three-input majority logic gate supported by near-memory operations, serving as a universal gate and achieving both robust reliability and high efficiency in versatile logic operations. We fabricated a highly reliable HfOx-based memristive array, incorporating a series resistor to increase the reset voltage of the memristor, thereby increasing the operational voltage margin of the gate operation. This ensured reliable operation of the majority gate, resulting in successful experimental proof of combined 1-bit full adder and subtractor operations performed in 5 steps using 7 cells. Additionally, we propose that an N-bit parallel prefix adder (PPA) operation is possible in O(log2 N) steps, by taking advantage of the parallel operation capability of the majority gate. This achieves 8.5× higher spatiotemporal efficiency than the previously reported NOR-based logic system in 64-bit adder operation. Moreover, as N increases, the spatiotemporal efficiency further improves, which significantly enhances the applicability of memristive logic-in-memory.

A 9T-SRAM in-memory computing macro for Boolean logic and multiply-and-accumulate operations

Artificial intelligence algorithms play important roles in image classification to speech recognition, which contains enormous Boolean logic and multiplication operations. Traditional von Neumann architecture separates computing and storage units, which leads to “power walls” and “memory walls” problems. In-memory computing (IMC) is a promising method to solve these problems. In this work, we propose an IMC macro based on customed 9T-SRAM, which can be configured in memory, Boolean logic and multiply-and-accumulate (MAC) modes. The 9T-SRAM adopts read/write decoupled and a tail transistor structure, which enhances the read stability and reduces power consumption. With the bias rows, Boolean logic results are obtained from the differential voltages on two bitlines, reducing the peripheral circuit for reference voltage generation. Furthermore, the bias rows replace analog to digital converter (ADC) to binarize the MAC result, reducing the area overhead. In a 55 nm process, simulations manifest the 9T-SRAM shows enhanced read static noise margin, and the macro exhibits stable IMC operations and high energy-efficiency.

Simulating an Integrated Photonic Image Classifier for Diffractive Neural Networks.

The slowdown of Moore's law and the existence of the "von Neumann bottleneck" has led to electronic-based computing systems under von Neumann's architecture being unable to meet the fast-growing demand for artificial intelligence computing. However, all-optical diffractive neural networks provide a possible solution to this challenge. They can outperform conventional silicon-based electronic neural networks due to the significantly higher speed of the propagation of optical signals (≈108 m.s-1) compared to electrical signals (≈105 m.s-1), their parallelism in nature, and their low power consumption. The integrated diffractive deep neural network (ID2NN) uses an on-chip fully passive photonic approach to achieve the functionality of neural networks (matrix-vector operations) and can be fabricated via the CMOS process, which is technologically more amenable to implementing an artificial intelligence processor. In this paper, we present a detailed design framework for the integrated diffractive deep neural network and corresponding silicon-on-insulator integration implementation through Python-based simulations. The performance of our proposed ID2NN was evaluated by solving image classification problems using the MNIST dataset.

Beyond zeros and ones – analog computing in the twenty-first century

Analog computing is often considered to be an outdated technology only to be found and cared for in museums but not as the basis of modern cutting edge computing. Nothing could be further from reality. Together with quantum computers, analog computers complement today's stored program digital computers, acting as co-processors for certain types of computationally intensive tasks. They are highly energy efficient and exhibit a degree of parallelism that by far surpasses classic digital computers. In contrast to quantum computers, analog computers do not require exotic technologies, no intricate cooling systems, no elaborate shielding systems, etc. In addition to this there already exists a plethora of proven programs for analog computers to solve a wide variety of problems. This paper describes the necessity of analog computing for the twenty-first century, gives a short introduction to the structure and programming of analog computers, before discussing future application areas. Analog computing will drastically alter the way we think about computing in the years to come as it will become an integral part of every high performance computer. It will be an indispensable technology for future AI systems, it will revolutionize many medical applications, it might even replace or at least complement, certain types of quantum computers, etc.

A novel time-domain in-memory computing unit using STT-MRAM

Advancements in technologies like Big Data, IoT, and AI have revealed a bottleneck in traditional von-Neumann architecture, resulting in high energy consumption and limited memory bandwidth. In-memory computing (IMC) presents a promising solution by enabling computations directly within the memory, enhancing energy-efficient computing. The existing time-domain (TD)-based IMC computations either require multiple cycles for computation through a successive read/write approach or contribute to the complexity of the peripheral circuit by adopting a cumulative delay approach. In this paper, we present a novel array architecture that utilizes spin transfer torque magnetic random access memory (STT-MRAM) bit-cells, mitigating source degeneration issue. By leveraging this advanced technology and employing a TD computing scheme, we have successfully implemented various arithmetic operations, alongside a comprehensive set of Boolean logic operations. Our design demonstrates improved area and energy efficiency compared to other existing TD computing schemes. Furthermore, despite the higher delay, our parameter-driven optimization approach efficiently minimizes it. To validate our proposal, we performed simulations using the 45 nm CMOS process and the Verilog-A based magnetic tunnel junction (MTJ) compact model. Through meticulous Monte-Carlo simulations, considering CMOS variations, the results demonstrate enhanced computational accuracy with increasing Tunnel Magnetoresistance (TMR) ratio, showcasing the potential of our architecture in advancing the field of computing.

Novel neuromorphic architectures based on crossbar arrays of (Co-Fe-B)<sub>x</sub>(LiNbO<sub>3</sub>)<sub>100−x</sub> nanocomposite memristors

Memristor-based neuromorphic computing systems (NСSs) provide a fast, high computational and energy efficient approach to neural network (NN) training and solving cognitive problems (pattern recognition, big data processing, prediction, etc.) [1]. Memristors could be organized in large crossbar arrays to perform vector-matrix multiplication (VMM) in a natural one-step way by the weighted electrical current summation (according to the Ohm’s and Kirchhoff’s laws) [1]. In contrast, being the most massively parallel operation in NN learning and inference, VMM is extremely time- and energy-expensive in traditional von Neumann architectures. Owing to this difference, memristor-based NCSs are of high interest. Memristors have already been successfully implemented for diverse NCS realizations, and such schemes as multi-layer perceptron (MLP) [2], long short-term memory and others have been demonstrated. Most of these NCSs are usually trained by various types of gradient descent learning algorithm, the hardware realization of which is challenging due to unreliable cycle-to-cycle (c2c) and device-to-device (d2d) variations of memristive devices. Several approaches have been proposed to partially mitigate these problems, including reservoir computing [3] and fine feature engineering [4]. The general idea of such approaches is to reduce the number of required weights (i.e. memristors) compared with fully connected NNs. In this respect, such novel architectures as convolutional NN (CNN) and MLP-mixer are of high interest as they provide significant weight reduction without classification efficiency drop. Although CNN based on memristors was already demonstrated, different aspects of its realization (such as hybrid hardware-software co-design) have yet to be studied. MLP-mixer was realized only in software. Therefore, in this work we have studied the possibility of hardware realization of CNN and MLP-mixer networks based on crossbar arrays of memristors. For this purpose, we studied (Co-Fe-B)x(LiNbO3)100−x nanocomposite (CFB-LNO NC) memristors, which operate through a multifilamentary resistive switching (RS) mechanism, demonstrate high endurance, long retention and possess multilevel RS [5]. Crossbar array of memristors was fabricated using laser photolithography for patterning electrode buses and ion-beam sputtering on the original facility for active layer deposition (~10 nm thick LiNbO3 and ~290 nm thick CFB-LNO NC with x ≈10–25 at.%). Details of the fabrication process could be found elsewhere [5]. I-V curves of the fabricated memristors showed small c2c and d2d variations, plasticity with 16 different resistive states and endurance of more than 105 cycles. Using the nanocomposite based crossbar arrays, we implemented a hybrid CNN, consisting of a hardware feature extractor with one/two kernels and a software classifier. Additionally, we have demonstrated in simulation that the usage of the memristors under study in the accurately adapted MLP-Mixer architecture results in high classification accuracy that is resilient to memristive variations and stuck devices.

Metal-Oxide Heterojunction: From Material Process to Neuromorphic Applications.

As technologies like the Internet, artificial intelligence, and big data evolve at a rapid pace, computer architecture is transitioning from compute-intensive to memory-intensive. However, traditional von Neumann architectures encounter bottlenecks in addressing modern computational challenges. The emulation of the behaviors of a synapse at the device level by ionic/electronic devices has shown promising potential in future neural-inspired and compact artificial intelligence systems. To address these issues, this review thoroughly investigates the recent progress in metal-oxide heterostructures for neuromorphic applications. These heterostructures not only offer low power consumption and high stability but also possess optimized electrical characteristics via interface engineering. The paper first outlines various synthesis methods for metal oxides and then summarizes the neuromorphic devices using these materials and their heterostructures. More importantly, we review the emerging multifunctional applications, including neuromorphic vision, touch, and pain systems. Finally, we summarize the future prospects of neuromorphic devices with metal-oxide heterostructures and list the current challenges while offering potential solutions. This review provides insights into the design and construction of metal-oxide devices and their applications for neuromorphic systems.

Analog memristive devices based on La2NiO4+ δ as synapses for spiking neural networks

Neuromorphic computing has recently emerged as a potential alternative to the conventional von Neumann computer paradigm, which is inherently limited due to its architectural bottleneck. Thus, new artificial components and architectures for brain-inspired computing hardware implementation are required. Bipolar analog memristive devices, whose resistance (or conductance) can be continuously tuned (as a synaptic weight), are potential candidates for artificial synapse applications. In this work, lanthanum nickelate (La2NiO4+δ , L2NO4), a mixed ionic electronic conducting oxide, is used in combination with TiN and Pt electrodes. The TiN/L2NO4/Pt devices show bipolar resistive switching with gradual transitions both for the SET and RESET processes. The resistance (conductance) can be gradually modulated by the pulse amplitude and duration, showing good data retention characteristics. A linear relationship between the resistance change and total applied pulse duration is experimentally measured. Moreover, synaptic depression and potentiation characteristics, one of the important functions of bio-synapses, are artificially reproduced for these devices, then modeled and successfully tested in a spiking neural network environment. These results indicate the suitability of using TiN/L2NO4/Pt memristive devices as long-term artificial synapses in neuromorphic computing.

Continuous variable port-based teleportation

Port-based teleportation (PBT) is a generalisation of the standard teleportation protocol which does not require unitary operations by the receiver. This comes at the price of requiring N > 1 entangled pairs, while N = 1 for the standard teleportation protocol. The lack of correction unitaries allows PBT to be used as a fundamental theoretical tool to simulate arbitrary channels with a general resource, with applications to study fundamental limits of quantum communication, cryptography and sensing, and to define general programmable quantum computers. Here we introduce a general formulation of port-based teleportation in continuous variable systems and study in detail the N = 2 case. In particular, we interpret the resulting channel as an energy truncation and analyse the kinds of channels that can be naturally simulated after this restriction.

Exploring Multi‐Bit Logic In‐Memory with Memristive HfO2‐Based Ferroelectric Tunnel Junctions

AbstractThe increasing demand for data movement and energy consumption in physically separate von Neumann architectures, where the processor and memory are distinct entities, highlights the severity of the memory‐wall problem. Thus, memristor‐based logic‐in‐memory (LiM) has garnered significant interest as it is a paradigm that enables both logic and memory functionalities to be performed within a single device. Ferroelectric tunnel junctions (FTJs) have the advantages of low energy consumption and high scalability; thus, they are particularly appropriate for use as analog memristors in LiMs. Precise and accurate programming of the analog resistance states in FTJs is essential to achieve an efficient memristor‐based LiM design. However, existing switching models for FTJs cannot completely consider the ferroelectric domain switching, which challenges multi‐bit LiM operations. This particularly applies in cases involving updates from one intermediate resistance state (IRS) to another IRS, such as transitioning from State 01 to 10 in 2‐bit LiM. In this study, a novel phenomenon associated with domain switching is observed in the IRS of an HZO FTJ device and applied it to an LiM implementation. These findings can contribute to the operational accuracy and update rules of not only FTJ‐based LiMs but also other FTJ applications, such as crossbar arrays.

Reconfigurable Physical Reservoir Enabled by Polarization of Ferroelectric Polymer P(VDF–TrFE) and Interface Charge‐Trapping/Detrapping in Dual‐Gate IGZO Transistor

AbstractNeuromorphic computers promise to enhance computing efficiency by eliminating conventional von Neumann architecture bottlenecks. Bio‐inspired artificial neural networks, such as feedforward neural networks and reservoir computing (RC), face challenges due to the unique memristor requirements. In this study, a dual‐gate ferroelectric polymer P(VDF–TrFE)‐coupled thin film transistor (DG–TFT) with an IGZO channel is presented. It yields complementary short‐ and long‐term memory functionalities are derived from the charge‐trapping/detrapping process at the IGZO‐SiO2 dielectric interface and ferroelectric polarization. These memory functionalities can be switched using different gated modes to meet the requirements of the reservoir and readout layers in RC. The bottom‐gated mode (BG‐mode) exhibits short‐term memory effects and nonlinear dynamics, whereas the top‐gated mode (TG‐mode) displays improved long‐term memory characteristics. To evaluate the long‐term memory properties, Python is used for pattern recognition. For the nonlinear dynamics and short‐term memory response of the BG‐mode, the DG–TFT is employed as a reservoir layer to handle various temporal tasks. Notably, the polarization level of the ferroelectric layer is coupled to improve the richness of the reservoir states, providing a reconfigurable RC system with an expanded capacity to effectively process and accommodate diverse signals. This holds potential for next‐generation hybrid intelligent applications.

Stochastic Adder Circuits with Improved Entropy Output.

Random pulse computing (RPC), the third paradigm along with digital and quantum computing, draws inspiration from biology, particularly the functioning of neurons. Here, we study information processing in random pulse computing circuits intended for the summation of numbers. Based on the information-theoretic merits of entropy budget and relative Kolmogorov-Sinai entropy, we investigate the prior art and propose new circuits: three deterministic adders with significantly improved output entropy and one exact nondeterministic adder that requires much less additional entropy than the previous art. All circuits are realized and tested experimentally, using quantum entropy sources and reconfigurable logic devices. Not only the proposed circuits yield a precise mathematical result and have output entropy near maximum, which satisfies the need for building a programmable random pulse computer, but also they provide affordable hardware options for generating additional entropy.

A large-scale integrated vector–matrix multiplication processor based on monolayer molybdenum disulfide memories

Data-driven algorithms—such as signal processing and artificial neural networks—are required to process and extract meaningful information from the massive amounts of data currently being produced in the world. This processing is, however, limited by the traditional von Neumann architecture with its physical separation of processing and memory, which motivates the development of in-memory computing. Here we report an integrated 32 × 32 vector–matrix multiplier with 1,024 floating-gate field-effect transistors that use monolayer molybdenum disulfide as the channel material. In our wafer-scale fabrication process, we achieve a high yield and low device-to-device variability, which are prerequisites for practical applications. A statistical analysis highlights the potential for multilevel and analogue storage with a single programming pulse, allowing our accelerator to be programmed using an efficient open-loop programming scheme. We also demonstrate reliable, discrete signal processing in a parallel manner.

Ultrafast SET/RESET operation for optoelectronic hybrid phase-change memory device cells based on Ge2Sb2Te5 material using partial crystallization strategy

Combination of nonvolatile storage and in-memory computing promises to break through the “memory bottleneck” that computing device adopts von Neumann architecture with individual computing and memory unit. Thus, the advanced nonvolatile memory device with ultrafast operation speed is urgently required. Here, the optoelectronic hybrid phase-change memory based on the Ge2Sb2Te5 material is proposed, where the picosecond laser induced reversible phase-change is utilized to write and erase the information while the resistance difference is adopted to realize the accurate information readout. Due to the significant difference in resistance between crystalline and amorphous states, a partial crystallization strategy can be adopted to achieve ultrafast SET operation. Results indicate that SET operation speed of the Ge2Sb2Te5 film and device unit can be as fast as 52 and 130 ps, respectively, while the RESET speed reaches 13 ps. In parallel, the resistance ratio of RESET to SET state is still as high as two orders of magnitude. By using partial crystallization strategy, the phase-change induced by picosecond laser only occurs from amorphous to face-centered-cubic crystalline state with low crystallinity and the defective octahedral motif is observed in the Ge2Sb2Te5 film, which is beneficial to achieve the ultrafast operation speed. At the same time, the ordered clusters existed in the as-deposited and picosecond laser induced RESET films can accelerate the nucleation process of the Ge2Sb2Te5 film, which is one of the important reasons for achieving ultrafast SET speed. The optoelectronic hybrid phase-change memory with ultrafast operation speed may be one of the promising solutions for the in-memory computing.

Hybrid Deep Learning Techniques for Securing Bioluminescent Interfaces in Internet of Bio Nano Things.

The Internet of bio-nano things (IoBNT) is an emerging paradigm employing nanoscale (~1-100 nm) biological transceivers to collect in vivo signaling information from the human body and communicate it to healthcare providers over the Internet. Bio-nano-things (BNT) offer external actuation of in-body molecular communication (MC) for targeted drug delivery to otherwise inaccessible parts of the human tissue. BNTs are inter-connected using chemical diffusion channels, forming an in vivo bio-nano network, connected to an external ex vivo environment such as the Internet using bio-cyber interfaces. Bio-luminescent bio-cyber interfacing (BBI) has proven to be promising in realizing IoBNT systems due to their non-obtrusive and low-cost implementation. BBI security, however, is a key concern during practical implementation since Internet connectivity exposes the interfaces to external threat vectors, and accurate classification of anomalous BBI traffic patterns is required to offer mitigation. However, parameter complexity and underlying intricate correlations among BBI traffic characteristics limit the use of existing machine-learning (ML) based anomaly detection methods typically requiring hand-crafted feature designing. To this end, the present work investigates the employment of deep learning (DL) algorithms allowing dynamic and scalable feature engineering to discriminate between normal and anomalous BBI traffic. During extensive validation using singular and multi-dimensional models on the generated dataset, our hybrid convolutional and recurrent ensemble (CNN + LSTM) reported an accuracy of approximately ~93.51% over other deep and shallow structures. Furthermore, employing a hybrid DL network allowed automated extraction of normal as well as temporal features in BBI data, eliminating manual selection and crafting of input features for accurate prediction. Finally, we recommend deployment primitives of the extracted optimal classifier in conventional intrusion detection systems as well as evolving non-Von Neumann architectures for real-time anomaly detection.

Power efficient MoS2 synaptic devices based on Maxwell–Wagner interfacial charging in binary oxides

Synaptic devices with tunable weight hold great promise in enabling non-von Neumann architecture for energy efficient computing. However, conventional metal-insulator-metal based two-terminal memristors share the same physical channel for both programming and reading, therefore the programming power consumption is dependent on the synaptic resistance states and can be particularly high when the memristor is in the low resistance states. Three terminal synaptic transistors, on the other hand, allow synchronous programming and reading and have been shown to possess excellent reliability. Here we present a binary oxide based three-terminal MoS2 synaptic device, in which the channel conductance can be modulated by interfacial charges generated at the oxide interface driven by Maxwell-Wagner instability. The binary oxide stack serves both as an interfacial charge host and gate dielectrics. Both excitatory and inhibitory behaviors are experimentally realized, and the presynaptic potential polarity can be effectively controlled by engineering the oxide stacking sequence, which is a unique feature compared with existing charge-trap based synaptic devices and provides a new tuning knob for controlling synaptic device characteristics. By adopting a three-terminal transistor structure, the programming channel and reading channel are physically separated and the programming power consumption can be kept constantly low (∼50 pW) across a wide dynamic range of 105. This work demonstrates a complementary metal oxide semiconductor compatible approach to build power efficient synaptic devices for artificial intelligence applications.

SpikeSim: An End-to-End Compute-in-Memory Hardware Evaluation Tool for Benchmarking Spiking Neural Networks

Spiking Neural Networks (SNNs) are an active research domain towards energy efficient machine intelligence. Compared to conventional artificial neural networks (ANNs), SNNs use temporal spike data and bio-plausible neuronal activation functions such as Leaky-Integrate Fire/Integrate Fire (LIF/IF) for data processing. However, SNNs incur significant dot-product operations causing high memory and computation overhead in standard von-Neumann computing platforms. To this end, In-Memory Computing (IMC) architectures have been proposed to alleviate the “memory-wall bottleneck" prevalent in von-Neumann architectures. Although recent works have proposed IMC-based SNN hardware accelerators, the following key implementation aspects have been overlooked 1) the adverse effects of crossbar non-ideality on SNN performance due to repeated analog dot-product operations over multiple time-steps 2) hardware overheads of essential SNN-specific components such as the LIF/IF and data communication modules. To this end, we propose SpikeSim, a tool that can perform realistic performance, energy, latency and area evaluation of IMC-mapped SNNs. SpikeSim consists of a practical monolithic IMC architecture called SpikeFlow for mapping SNNs. Additionally, the non-ideality computation engine (NICE) and energy-latency-area (ELA) engine performs hardware-realistic evaluation of SpikeFlow-mapped SNNs. Based on 65nm CMOS implementation and experiments on CIFAR10, CIFAR100 and TinyImagenet datasets, we find that the LIF/IF neuronal module has significant area contribution (>11% of the total hardware area). To this end, we propose SNN topological modifications that leads to 1.24× and 10× reduction in the neuronal module’s area and the overall energy-delay-product value, respectively. Furthermore, in this work, we perform a holistic comparison between IMC implemented ANN and SNNs and conclude that lower number of time-steps are the key to achieve higher throughput and energy-efficiency for SNNs compared to 4-bit ANNs. The code repository for the SpikeSim tool is available at https://github.com/Intelligent-Computing-Lab-Yale/Quanitzation-aware-SNN-training-and-hardware-evaluation-for-IMC-Architectures

MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures

In the age of Artificial Intelligence (AI), the huge data movements between memory and computing units become the bottleneck of von Neumann architectures, i.e., the “memory wall” problem. In order to tackle this challenge, Processing-In-Memory (PIM) architectures are proposed, which perform in-situ computations in memory and give alternative solutions to boost the computing energy efficiency and performance. Because of the large-scale Neural Network (NN) algorithm models and the huge hardware design space, various factors affect computing accuracy and performance, bringing the need for efficient PIM modeling and evaluation tools. In this work, we propose a behavior-level modeling tool, MNSIM 2.0, to model the performance of PIM architectures efficiently. At the hardware level, MNSIM 2.0 provides a hierarchical PIM modeling structure with flexible architecture configurability and components extensibility. Moreover, the first unified PIM memory array model is proposed for describing both digital and analog PIM. At the algorithm level, MNSIM 2.0 supports the PIM-based NN computing accuracy simulation considering various architecture and device parameters. A PIM-oriented NN model training and quantization flow is also integrated to improve the performance gain brought by PIM. At the scheduling level, MNSIM 2.0 adopts a universal scheduling description compatible with different scheduling strategies. Validation using fabricated PIM macros shows the relative modeling error rate of MNSIM 2.0 is 3:8 5:5%. Case studies show that MNSIM 2.0 enables PIM design space explorations, influences analysis of device parameters, and architecture design insight discoveries.

STREAM: Toward READ-Based In-Memory Computing for Streaming-Based Processing for Data-Intensive Applications

With the rise of data intensive applications, traditional computing paradigms have hit the memory-wall. In-memory computing using emerging non-volatile memory (NVM) technology is a promising solution strategy to overcome the limitations of the von-Neumann architecture. In-memory computing using NVM devices has been explored in both analog and digital domains. Analog in-memory computing can perform matrix-vector multiplication (MVM) in an extremely energy-efficient manner. However, analog in-memory computing is prone to errors and resulting precision is therefore low. On the contrary, digital in-memory computing is a viable option for accelerating scientific computations that require deterministic precision. In recent years, several digital in-memory computing styles have been proposed. Unfortunately, state-of-the-art digital in-memory computing styles rely on repeated WRITE operations which involves switching of NVM devices. WRITE operations in NVM cells are expensive in terms of energy, latency and device endurance. In this paper, we propose a READ-based in-memory computing framework called STREAM. The framework performs streaming-based data processing for data-intensive applications. The STREAM framework consists of a synthesis tool that decomposes an arbitrary Boolean function into in-memory compute kernels. Two synthesis approaches are proposed to generate READ-based in-memory compute kernels using data structures from logic synthesis. A hardware/software co-design technique is developed to minimize the inter-crossbar data communication. The STREAM framework is evaluated using circuits from ISCAS85 benchmark suite, and Suite-Sparse applications to scientific computing. Compared with state-of-the-art in-memory computing framework, the proposed framework improves latency and energy performance with up to 200X and 20X, respectively.

FeFET-Based In-Memory Hyperdimensional Encoding Design

The data explosion of Internet-of-Things (IoTs) and machine learning tasks raises a great demand on highly efficient computing hardware and paradigms. Brain-inspired hyperdimensional computing (HDC) is becoming a promising computing paradigm, which encodes data as hypervectors with homogeneous elements instead of numbers, and can perform learning/classification tasks through simple logical or arithmetic operations on the encoded hypervectors. Therefore HDC has much lower computational complexity than conventional computational models such as neural networks. However, due to its high-dimensional data representation, processing and encoding hypervectors in conventional Von-Neumann architectures (e.g., CPU and GPU) requires a large amount of energy-and time-consuming data transfer, thus weakening its efficiency benefiting from low complexity. In this paper, we proposed an ultra-low power and fast computing-in-Memory (CiM) design based on non-volatile (NV) Ferroelectric FET (FeFET) for HDC encoding. The proposed design mainly support hyperdimensional bit-wise XOR and parallel majority vote (MAJ) operations for HDC encoding, which are implemented by FeFET based memories together with CMOS peripheral circuits. The 1FeFET1T based memory cell effectively mitigates the impact of transistor variations on the operation. A highly parallel and pipelined computing workflow of the proposed design further boosts the energy efficiency and performance with negligible extra area overhead. Experimental results demonstrate that our proposed design achieves 5.04× energy efficiency improvement over other CiM designs for HDC encoding.