FeFET-Based In-Memory Hyperdimensional Encoding Design

Abstract

The data explosion of Internet-of-Things (IoTs) and machine learning tasks raises a great demand on highly efficient computing hardware and paradigms. Brain-inspired hyperdimensional computing (HDC) is becoming a promising computing paradigm, which encodes data as hypervectors with homogeneous elements instead of numbers, and can perform learning/classification tasks through simple logical or arithmetic operations on the encoded hypervectors. Therefore HDC has much lower computational complexity than conventional computational models such as neural networks. However, due to its high-dimensional data representation, processing and encoding hypervectors in conventional Von-Neumann architectures (e.g., CPU and GPU) requires a large amount of energy-and time-consuming data transfer, thus weakening its efficiency benefiting from low complexity. In this paper, we proposed an ultra-low power and fast computing-in-Memory (CiM) design based on non-volatile (NV) Ferroelectric FET (FeFET) for HDC encoding. The proposed design mainly support hyperdimensional bit-wise XOR and parallel majority vote (MAJ) operations for HDC encoding, which are implemented by FeFET based memories together with CMOS peripheral circuits. The 1FeFET1T based memory cell effectively mitigates the impact of transistor variations on the operation. A highly parallel and pipelined computing workflow of the proposed design further boosts the energy efficiency and performance with negligible extra area overhead. Experimental results demonstrate that our proposed design achieves 5.04× energy efficiency improvement over other CiM designs for HDC encoding.