Generation Of Processors Research Articles

A NUMA-Aware Version of an Adaptive Self-Scheduling Loop Scheduler

Parallelizing code in a shared-memory environment is commonly done utilizing loop scheduling (LS) in a fork-join manner as in OpenMP. This manner of parallelization is popular due to its ease to code, but the choice of the LS method is important when the workload per iteration is highly variable. Currently, the shared-memory environment is evolving in high-performance computing as larger chiplet-based processors with high core counts and segmented L3 cache are introduced. These processors have a stronger non-uniform memory access (NUMA) effect than the previous generation of x86-64 processors. This work attempts to modify the adaptive self-scheduling loop scheduler known as iCh ( i rregular Ch unk) for these NUMA environments while analyzing the impact of these systems on default OpenMP LS methods. In particular, iCh is as a default LS method for irregular applications (i.e., applications where the workload per iteration is highly variable) that guarantees “good” performance without tuning. The modified version, named NiCh , is demonstrated over multiple irregular applications to show the variation in performance. The work demonstrates that NiCh is able to better handle architectures with stronger NUMA effects, and particularly is better than iCh when the number of threads is greater than the number of cores. However, NiCh also comes with being less universally “good” than iCh and a set of parameters that are hardware dependent.

Subjective evaluation of the benefits of the Samba 2 Vibrant Soundbridge middle ear implant processor compared to the older generation processors

Subjective evaluation of the benefits of the Samba 2 Vibrant Soundbridge middle ear implant processor compared to the older generation processors

Charge-parity switching effects and optimisation of transmon-qubit design parameters

Enhancing the performance of noisy quantum processors requires improving our understanding of error mechanisms and the ways to overcome them. A judicious selection of qubit design parameters plays a pivotal role in improving the performance of quantum processors. In this study, we identify optimal ranges for qubit design parameters, grounded in comprehensive noise modeling. To this end, we also analyze the effect of a charge-parity switch caused by quasiparticles on a two-qubit gate. Due to the utilization of the second excited state of a transmon, where the charge dispersion is significantly larger, a charge-parity switch will affect the conditional phase of the two-qubit gate. We derive an analytical expression for the infidelity of a diabatic controlled-Z gate and see effects of similar magnitude in adiabatic controlled-phase gates in the tunable coupler architecture. Moreover, we show that the effect of a charge-parity switch can be the dominant quasiparticle-related error source of a two-qubit gate. We also demonstrate that charge-parity switches induce a residual longitudinal interaction between qubits in a tunable-coupler circuit. Furthermore, we introduce a performance metric for quantum circuit execution, encompassing the fidelity and number of single- and two-qubit gates in an algorithm, as well as the state preparation fidelity. This comprehensive metric, coupled with a detailed noise model, enables us to determine an optimal range for the qubit design parameters, as confirmed by numerical simulation. Our systematic analysis offers insights and serves as a guiding framework for the development of the next generation of transmon-based quantum processors.

Magnetization reversal by multiple optical pulses for a photonic spiking neuron with the leaky integrate and fire model

Photonic accelerators are anticipated to be the next generation of hardware processors, replacing traditional electronic accelerators. In current photonic accelerators based on artificial neural networks, photonic integrated circuits are incorporated with electronic integrated circuits to leverage their strengths: photonic circuits are used to perform linear calculations, while electronic circuits are used to perform nonlinear calculations. However, this architecture requires optoelectric conversion at each layer and is unable to leverage the superiority of light. We propose a novel photonic spiking neuron with a magneto-optical synapse and an all-optical spiking neural network. This study experimentally demonstrates that the magnetization reversal of CoFeB, which occurs during thermal accumulation owing to multiple optical pulses, is similar to the behavior of the leaky integrated and fire model of spiking neurons.

Advances in Packaging Crucial to Powering Next Generation Processors [From the Editor]

Advances in Packaging Crucial to Powering Next Generation Processors [From the Editor]

Avoiding barren plateaus in the variational determination of geometric entanglement

The barren plateau (BP) phenomenon is one of the main obstacles to implementing variational quantum algorithms in the current generation of quantum processors. Here, we introduce a method capable of avoiding the BP phenomenon in the variational determination of the geometric measure of entanglement for a large number of qubits. The method is based on measuring compatible two-qubit local functions whose optimization allows for achieving a well-suited initial condition from which a global function can be further optimized without encountering a BP. We analytically demonstrate that the local functions can be efficiently estimated and optimized. Numerical simulations up to 18 qubit GHZ and W states demonstrate that the method converges to the exact value. In particular, the method allows for escaping from BPs induced by hardware noise or global functions defined on high-dimensional systems. Numerical simulations with noise agree with experiments carried out on IBM’s quantum processors for seven qubits.

Optofluidic passive parity-time-symmetric systems.

This research introduces a novel methodology of harnessing liquids to facilitate the realization of parity-time (PT)-symmetric optical waveguides on highly integrated microscale platforms. Additionally, we propose a realistic and detailed fabrication process flow, demonstrating the practical feasibility of fabricating our optofluidic system, thereby bridging the gap between theoretical design and actual implementation. Extensive research has been conducted over the past two decades on PT-symmetric systems across various fields, given their potential to foster a new generation of compact, power-efficient sensors and signal processors with enhanced performance. Passive PT-symmetry in optics can be achieved by evanescently coupling two optical waveguides and incorporating an optically lossy material into one of the waveguides. The essential coupling distance between two optical waveguides in air is usually less than 500 nm for near-infrared wavelengths and under 100 nm for ultraviolet wavelengths. This necessitates the construction of the coupling region via expensive and time-consuming electron beam lithography, posing a significant manufacturing challenge for the mass production of PT-symmetric optical systems. We propose a solution to this fabrication challenge by introducing liquids capable of dynamic flow between optical waveguides. This technique allows the attainment of evanescent wave coupling with coupling gap dimensions compatible with standard photolithography processes. Consequently, this paves the way for the cost-effective, rapid and large-scale production of PT-symmetric optofluidic systems, applicable across a wide range of fields.

Pulse-efficient quantum machine learning

Quantum machine learning algorithms based on parameterized quantum circuits are promising candidates for near-term quantum advantage. Although these algorithms are compatible with the current generation of quantum processors, device noise limits their performance, for example by inducing an exponential flattening of loss landscapes. Error suppression schemes such as dynamical decoupling and Pauli twirling alleviate this issue by reducing noise at the hardware level. A recent addition to this toolbox of techniques is pulse-efficient transpilation, which reduces circuit schedule duration by exploiting hardware-native cross-resonance interaction. In this work, we investigate the impact of pulse-efficient circuits on near-term algorithms for quantum machine learning. We report results for two standard experiments: binary classification on a synthetic dataset with quantum neural networks and handwritten digit recognition with quantum kernel estimation. In both cases, we find that pulse-efficient transpilation vastly reduces average circuit durations and, as a result, significantly improves classification accuracy. We conclude by applying pulse-efficient transpilation to the Hamiltonian Variational Ansatz and show that it delays the onset of noise-induced barren plateaus.

Liquid‐Core Optical Fibers—A Dynamic Platform for Nonlinear Photonics

AbstractSoftphotonics has emerged as a new discipline that utilizes soft matter (i.e., liquids, gels, bio‐materials) as waveguide materials with versatile functionalities. The flexible properties of soft matter show great potential for further exploiting nonlinear in‐fiber phenomena to gain more insights into their fundamental dynamics and to inspire a new generation of broadband optical light sources and signal processors that are adaptable, reconfigurable, and biocompatible. In particular, incorporating solvents with extraordinary temperature sensitivity, miscibility, and nonlinearity into optical fibers has spawned a series of inventions and fundamental scientific findings over the last decades. This review highlights the current state of development of nonlinear photonics in liquid‐filled fibers. The current state of knowledge in the linear and nonlinear material properties of the most prominent solvents (CS2, CCl4, C2Cl4, benzene and its derivatives) are revisited, and recent advances in nonlinear liquid‐core fiber optics, including a special highlight on phenomena that are unique to liquids, such as modified solitary states and local dispersion control are summarized. Finally, the leading scientific challenges for advancing the field, which highlights liquid‐core fibers as a rich platform for science and technology, are discussed.

Thales alenia space 6 th generation digital transparent processor (DTP6G) - a multi-mission, multi-mode versatile product at the heart of telecom solutions

Flexibility and in-flight reconfigurability offered by digital processing have become key features in today's telecom satellite payloads. In recent years, Thales Alenia Space has developed several generations of on-board digital transparent processors (DTP) by introducing the most advanced and disruptive technologies. Thales Alenia Space DTPs are state-of-the-art sub-systems at the heart of payloads using analogue-to-digital (ADC) and digital-to-analogue (DAC) channelizers on their input and output RF accesses and making extensive use of digital processing to support channel routing with fine bandwidth granularity. After several payloads based on 5th generation processors, Space Inspire (INstant SPace In-orbit REconfiguration)) solution uses a 6th generation processors offering another step in flexibility through Digital Beam Forming (DBFN). This latest processor generation leverages DTP3G and 5G assets as well as in-flight heritage and provides many more features. Developped with support of CNES & DGA (French DoD), DTP6G covers Civil but also MilsatCom/GovSatCom missions thanks to high performances and small routing granularity. Its main current usecases are GEO but it is compatible with LEO to MEO orbits. Although DBFN is a key addition of DTP6G, it can still be operated with fixed-beam antennas or with an analog BFN. Another new feature is the embedded High Speed Command/Control link (HiLink) providing high TMTC throughput over several waveforms (Full CCSDS or CCSDS over DVBS2). Internal encryption is proposed (AES) but access to an external encryption unit (NSA-type) is also possible. This C&C link combined with a high-performance/large-storage-capacity processing board ensures fast operability and a high-level of observability. DTP6G processor is also ready for future implementations of a Regenerative companion, Beamhopping and Multi-user scenarios. The paper will present Thales Alenia Space transparent processor roadmap leading to DTP6G, its mission coverage, main features and a status of development & production.

Scalable and ultralow power silicon photonic two-dimensional phased array

Photonic integrated circuit based optical phased arrays (PIC-OPAs) are emerging as promising programmable processors and spatial light modulators, combining the best of planar and free-space optics. Their implementation on silicon photonic platforms has been especially fruitful. Despite much progress in this field, demonstrating steerable two-dimensional (2D) OPAs that are scalable to a large number of array elements and operate with a single wavelength has proven a challenge. In addition, the phase shifters used in the array for programming the far-field beam are either power hungry or have a large footprint, preventing the implementation of large scale 2D arrays. Here, we demonstrate a two-dimensional silicon photonic phased array with high-speed (∼330 kHz) and ultralow power microresonator phase-shifters with a compact radius (∼3 µm) and 2π phase shift ability. Each phase-shifter consumes an average of ∼250 µW of static power for resonance alignment and ∼50 µW of power for far-field beamforming, a more than one order of magnitude improvement compared to prior OPA works based on waveguide-based thermo-optic phase shifters. Such PIC-OPA devices can enable a new generation of compact and scalable low power processors and sensors.

Native qudit entanglement in a trapped ion quantum processor

Quantum information carriers, just like most physical systems, naturally occupy high-dimensional Hilbert spaces. Instead of restricting them to a two-level subspace, these high-dimensional (qudit) quantum systems are emerging as a powerful resource for the next generation of quantum processors. Yet harnessing the potential of these systems requires efficient ways of generating the desired interaction between them. Here, we experimentally demonstrate an implementation of a native two-qudit entangling gate up to dimension 5 in a trapped-ion system. This is achieved by generalizing a recently proposed light-shift gate mechanism to generate genuine qudit entanglement in a single application of the gate. The gate seamlessly adapts to the local dimension of the system with a calibration overhead that is independent of the dimension.

The Expanding Role of Artificial Intelligence in Collaborative Robots for Industrial Applications: A Systematic Review of Recent Works

A collaborative robot, or cobot, enables users to work closely with it through direct communication without the use of traditional barricades. Cobots eliminate the gap that has historically existed between industrial robots and humans while they work within fences. Cobots can be used for a variety of tasks, from communication robots in public areas and logistic or supply chain robots that move materials inside a building, to articulated or industrial robots that assist in automating tasks which are not ergonomically sound, such as assisting individuals in carrying large parts, or assembly lines. Human faith in collaboration has increased through human–robot collaboration applications built with dependability and safety in mind, which also enhances employee performance and working circumstances. Artificial intelligence and cobots are becoming more accessible due to advanced technology and new processor generations. Cobots are now being changed from science fiction to science through machine learning. They can quickly respond to change, decrease expenses, and enhance user experience. In order to identify the existing and potential expanding role of artificial intelligence in cobots for industrial applications, this paper provides a systematic literature review of the latest research publications between 2018 and 2022. It concludes by discussing various difficulties in current industrial collaborative robots and provides direction for future research.

FPGA Implementation of Double Precision Floating Point Multiplier

High speed computation is the need of today’s generation of Processors. To accomplish this major task, many functions are implemented inside the hardware of the processor rather than having software computing the same task. Majority of the operations which the processor executes are Arithmetic operations which are widely used in many applications that require heavy mathematical operations such as scientific calculations, image and signal processing. Especially in the field of signal processing, multiplication division operation is widely used in many applications. The major issue with these operations in hardware is that much iteration is required which results in slow operation while fast algorithms require complex computations within each cycle. The result of a Division operation results in a either in Quotient and Remainder or a Floating point number which is the major reason to make it more complex than Multiplication operation.

New technology can benefit established middle ear implant users: Samba 2 vs previous models of audio processors for Vibrant Soundbridge

IntroductionThe Vibrant Soundbridge (VSB) is a semi-implantable hearing aid for patients with various types of hearing loss and has been available for over 25 years. Recently, new audio processors with advanced signal processing, noise reduction, and multi-microphone technology have appeared. The aim of this study is to compare the benefits of using the newest Samba 2 processor to the previous generation processors in a group of experienced VSB users.MethodsThere were 22 experienced VSB users (mean time of using VSB was 9 years, SD = 2) who had their processor (D404 or Amadé) upgraded to the newest model (Samba 2). The mean age of the subjects was 56 years (SD = 20). Assessments were made by free-field audiometry, speech reception in quiet and noise, and Patient-Reported Outcome Measures (PROMs).ResultsHearing tests in free field showed statistically significant improvements in hearing sensitivity and speech discrimination in quiet and noise with the Samba 2 audio processor compared to the earlier technology. PROMs confirmed the benefits of using the newest audio processor and there was more satisfaction in terms of usability.ConclusionsAccess to modern technology for VSB patients provides measurable benefits.

Metropolitan single-photon distribution at 1550 nm for random number generation

Quantum communication networks will connect future generations of quantum processors, enable metrological applications, and provide security through quantum key distribution. We present a testbed that is part of the municipal fiber network in the greater Stockholm metropolitan area for quantum resource distribution through a 20 km long fiber based on semiconductor quantum dots emitting in the telecom C-band. We utilize the service to generate random numbers passing the NIST test suite SP800-22 at a subscriber 8 km outside of the city with a bit rate of 23.4 kbit/s.

3 Paths to 3D Processors

A crop of high-performance processors is showing that the new direction for continuing Moore's Law is all about up. Each processor generation needs to perform better than the last, and at its most basic, that means integrating more logic onto the silicon. But there are two problems. The first is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The second is that individual chips have reached their size limits. Photolithography tools can pattern an area no larger than about 850 square millimeters, which is about the size of a modern server GPU. ▣ One answer has been to place two or more pieces of silicon side by side in the same package and stitch them together using millimeters-long, dense interconnects, so they can effectively act as a single unit. This so-called 2.5D scheme, enabled by advanced packaging technology, is already behind several top processors, which are now composed of several functional “chiplets” rather than a single IC. ▣ But to sling truly huge volumes of data around as if it were all on the same chip, you need even shorter and denser connections, and that can be done only by stacking one chip atop another. Connecting two chips face-to-face in a 3D scheme can mean making hundreds or thousands of micrometers-long connections per square millimeter. These short, dense connections let data zip from one piece of silicon to another almost as rapidly and with as little energy as if the two were one chip. ▣ It's taken a lot of innovation to get it to work. Engineers had to figure out how to keep heat from one chip in the stack from killing the other, decide what functions should go where and how they should be manufactured, keep the occasional bad chip from leading to a lot of costly dud systems, and deal with the resulting added complexities of doing all that at once. ▣ Here are three examples that show not just how 3D chip stacking is done but also what it's good for.

Arbitrary controlled-phase gate on fluxonium qubits using differential ac Stark shifts

Large scale quantum computing motivates the invention of two-qubit gate schemes that not only maximize the gate fidelity but also draw minimal resources. In the case of superconducting qubits, the weak anharmonicity of transmons imposes profound constraints on the gate design, leading to increased complexity of devices and control protocols. Here we demonstrate a resource-efficient control over the interaction of strongly-anharmonic fluxonium qubits. Namely, applying an off-resonant drive to noncomputational transitions in a pair of capacitively-coupled fluxoniums induces a $\text{ZZ}$ interaction due to unequal ac Stark shifts of the computational levels. With a continuous choice of frequency and amplitude, the drive can either cancel the static $\text{ZZ}$ term or increase it by an order of magnitude to enable a controlled-phase (CP) gate with an arbitrary programmed phase shift. The cross-entropy benchmarking of these non-Clifford operations yields a sub $1%$ error, limited solely by incoherent processes. Our result demonstrates the advantages of strongly-anharmonic circuits over transmons in designing the next generation of quantum processors.

Hierarchical Clustering of Power Models for circuits design

The work presented in this paper is part of a project which focuses on capitalization and reuse of power models used at Intel to calculate power consumption of electronic devices. These models are analytical and created using an application called IDPA (Intel® Docea™ Power Analytics). Hundreds of thousands of power models have been accumulated in a directory of files and folders, for the simulation of the consumption of thousands of products.The objective of this work is to group together the models that have been used for the same product, or the same family of products, for example a generation of processors. This notion of project is not present in the current version of the application, and we want to use clustering techniques to make proposals to users wishing to reuse groups of models already present in IDPA database, for example to design the next generation from the current one.To do that, agglomerative hierarchical clustering is used. Three features are considered to calculate the distance between files in which power models are stored: low delay between files’ edition times, similarity of files’ names and closeness in filesystem. Hence, we build a tool that can help architects to automatically group their power models into working projects. The proposition made by the algorithm can be refined by an expert or can be directly used by novice users to get an idea on a project on which they have no prior knowledge.

Speech perception and hearing effort using a new active middle ear implant audio processor

PurposeThe Vibrant Soundbridge (VSB) was introduced in 1996, and the fourth generation of the audio processor recently released. This clinical study evaluates the audiological performance and subjective satisfaction of the new SAMBA 2 audio processor compared to its predecessor, SAMBA.MethodFifteen VSB users tested both audio processors for approximately 3 weeks. Air conduction and bone conduction thresholds and unaided and aided sound field thresholds were measured with both devices. Speech performance in quiet (Freiburg monosyllables) and noise (OLSA) was evaluated as well as subjective listening effort (ACALES) and questionnaire outcomes (SSQ12 and APSQ). In addition, data from 16 subjects with normal hearing were gathered on sound field tests and ACALES.ResultsBoth audio processors showed substantial improvement compared to the unaided condition. The SAMBA and SAMBA 2 had comparable performance in sound filed thresholds, while the SAMBA 2 was significantly better in speech in quiet, speech in noise, reduced listening effort, and improved subjective satisfaction compared with the SAMBA.ConclusionThe SAMBA 2 audio processor, compared to its predecessor SAMBA, offers improved performance throughout the parameters investigated in this study. Patients with a VSB implant would benefit from an upgrade to SAMBA 2.