Hierarchical Clustering of Power Models for circuits design

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The work presented in this paper is part of a project which focuses on capitalization and reuse of power models used at Intel to calculate power consumption of electronic devices. These models are analytical and created using an application called IDPA (Intel® Docea™ Power Analytics). Hundreds of thousands of power models have been accumulated in a directory of files and folders, for the simulation of the consumption of thousands of products.The objective of this work is to group together the models that have been used for the same product, or the same family of products, for example a generation of processors. This notion of project is not present in the current version of the application, and we want to use clustering techniques to make proposals to users wishing to reuse groups of models already present in IDPA database, for example to design the next generation from the current one.To do that, agglomerative hierarchical clustering is used. Three features are considered to calculate the distance between files in which power models are stored: low delay between files’ edition times, similarity of files’ names and closeness in filesystem. Hence, we build a tool that can help architects to automatically group their power models into working projects. The proposition made by the algorithm can be refined by an expert or can be directly used by novice users to get an idea on a project on which they have no prior knowledge.