Generation Of Processors Research Articles

Everyday listening questionnaire: Correlation between subjective hearing and objective performance

ObjectivesClinical experience has demonstrated that speech understanding by cochlear implant (CI) recipients has improved over recent years with the development of new technology. The Everyday Listening Questionnaire 2 (ELQ 2) was designed to collect information regarding the challenges faced by CI recipients in everyday listening. The aim of this study was to compare self-assessment of CI users using ELQ 2 with objective speech recognition measures and to compare results between users of older and newer coding strategies.MethodsDuring their regular clinical review appointments a group of representative adult CI recipients implanted with the Advanced Bionics implant system were asked to complete the questionnaire. The first 100 patients who agreed to participate in this survey were recruited independent of processor generation and speech coding strategy. Correlations between subjectively scored hearing performance in everyday listening situations and objectively measured speech perception abilities were examined relative to the speech coding strategies used.ResultsWhen subjects were grouped by strategy there were significant differences between users of older ‘standard’ strategies and users of the newer, currently available strategies (HiRes and HiRes 120), especially in the categories of telephone use and music perception. Significant correlations were found between certain subjective ratings and the objective speech perception data in noise.ConclusionsThere is a good correlation between subjective and objective data. Users of more recent speech coding strategies tend to have fewer problems in difficult hearing situations.

Spiral in scala

Program generators for high performance libraries are an appealing solution to the recurring problem of porting and optimizing code with every new processor generation, but only few such generators exist to date. This is due to not only the difficulty of the design, but also of the actual implementation, which often results in an ad-hoc collection of standalone programs and scripts that are hard to extend, maintain, or reuse. In this paper we ask whether and which programming language concepts and features are needed to enable a more systematic construction of such generators. The systematic approach we advocate extrapolates from existing generators: a) describing the problem and algorithmic knowledge using one, or several, domain-specific languages (DSLs), b) expressing optimizations and choices as rewrite rules on DSL programs, c) designing data structures that can be configured to control the type of code that is generated and the data representation used, and d) using autotuning to select the best-performing alternative. As a case study, we implement a small, but representative subset of Spiral in Scala using the Lightweight Modular Staging (LMS) framework. The first main contribution of this paper is the realization of c) using type classes to abstract over staging decisions, i.e. which pieces of a computation are performed immediately and for which pieces code is generated. Specifically, we abstract over different complex data representations jointly with different code representations including generating loops versus unrolled code with scalar replacement - a crucial and usually tedious performance transformation. The second main contribution is to provide full support for a) and d) within the LMS framework: we extend LMS to support translation between different DSLs and autotuning through search.

The ACROSS MPSoC – A new generation of multi-core processors designed for safety–critical embedded systems

The European ARTEMIS ACROSS project aims to overcome the limitations of existing Multi-Processor Systems-on-a-Chip (MPSoC) architectures with respect to safety–critical applications. MPSoCs have a tremendous potential in the domain of embedded systems considering their enormous computational capacity and energy efficiency. However, the currently existing MPSoC architectures have significant limitations with respect to safety–critical applications. These limitations include difficulties in the certification process due to the high complexity of MPSoCs, the lacking temporal determinism and problems related to error propagation between subsystems. These limitations become even more severe, when subsystems of different criticality levels have to be integrated on the same computational platform. Examples of such mixed-criticality integration are found in the avionics and automotive industry with their desire to integrate safety–critical, mission critical and non-critical subsystems on the same platform in order to minimize size, weight, power and cost. The main objective of ACROSS is to develop a new generation of multi-core processors designed specially for safety–critical embedded systems; the ACROSS MPSoC. In this paper we will show how the ACROSS MPSoC overcomes the limitations of existing MPSoC architectures in order to make the multi-core technology available to the safety–critical domain. The proposed approach enables efficient certification, complexity management, mixed-criticality integration and the development of temporally deterministic hard real-time systems. The major technological innovations of ACROSS are an increased level of design abstraction, message-based interfaces for core-to-core communication and reliable fault and error containment established by a novel time-triggered network-on-chip. The achieved results comprise, a novel architecture for MPSoCs, a prototype implemenation on FPGA technology as a proof-of-concept, a comprehensive set of middle-ware services and multiple demonstrators that show the benefits of the ACROSS Architecture in real world industrial applications.

High performance computing tools in science and engineering

The combination of multicore architectures with the potential acceleration of Graphics Processing Units allows to design, low cost, desktop machines with hundreds of processing cores and at the same time to build large supercomputers with hundreds of thousands of computational units. Heterogeneity in the architecture and programming model appears naturally, so that the solution of many problems in science and engineering poses a different performance depending on the architecture and how they were programmed. Since current compilers are no longer able of automatically moving the computing power of the new generation of processors to applications, an interdisciplinary effort among researchers in science and engineering, and computing disciplines is demanded. The purpose of the Minisymposium on High Performance Computing in Science and Engineering is to bring together applied mathematicians, computer scientists, and in general researchers with costly applications or a fair knowledge/interest in high performance computing, to present, share, and discuss their techniques, tools, and ideas in the area of high performance computing applied to complex large-scale computational problems. This Minisymposium use is to be held as part of the International Conference on Computational and Mathematical Methods in Science and Engineering (CMMSE). This special issue collects a selection of the papers presented at the edition celebrated in La Manga del Mar Menor (Murcia–Spain) in July 2012 during the CMMSE—2012. Although several groupings of the contributions appearing in this issue can be performed, we decided to classify them into the four following groups.

Upgrade of a multi-channel active noise control system for an industrial stack

Active noise control has been studied in the 1990s as an innovative way to reduce the noise in specific situations. Some applications are well known today and found commercial success like noise-canceling headphones. However, the use of active noise control in industrial applications is more complex, thus being an uncommon solution in this field. The use of active noise control for industrial stack noise is one of these applications. One of the first large-scale implementation has been set up at the end of the 1990s. This system was a 10-channel active noise control system installed on a 1.8 m wide chimney to attenuate a 320 Hz pure tone. At that time, an 8 dB noise reduction was achieved at error microphones. Fifteen years later, it has been decided to upgrade the system with the latest generation of digital signal processor (DSP) allowing a real-time optimization and better tracking speed. This paper describes the overall system and the updated multi-channel active noise controller developed for this application. It also presents the improvements, the achieved noise reduction, and the associated environmental benefits.

Process Placement in Multicore Clusters:Algorithmic Issues and Practical Techniques

Current generations of NUMA node clusters feature multicore or manycore processors. Programming such architectures efficiently is a challenge because numerous hardware characteristics have to be taken into account, especially the memory hierarchy. One appealing idea to improve the performance of parallel applications is to decrease their communication costs by matching the communication pattern to the underlying hardware architecture. In this paper, we detail the algorithm and techniques proposed to achieve such a result: first, we gather both the communication pattern information and the hardware details. Then we compute a relevant reordering of the various process ranks of the application. Finally, those new ranks are used to reduce the communication costs of the application.

A Dedicated Micro-Kernel to Combine Real-Time and Stream Applications on Embedded Manycores

The latest generation of many-core processors offers more than ever the opportunity to pool different applications into a single embedded system. This opportunity however depends on the ability to provide safety guarantees, especially when it comes to embedded life- or mission-critical applications.For that matter, we introduce a new multi-task preemptive micro-kernel for many-core architectures called Psigma. This micro-kernel is able to run simultaneously and safely tasks written with very different programming paradigm, and very differ- ent execution requirements: hard real-time applications and stream applications. This paper shortly presents both programming models, then focuses on the design and performances of the micro-kernel.

Development and VLSI implementation of a data security scheme for RFID system using programmable cellular automata

Data security is a critical issue for Radio Frequency Identification (RFID) system as it hides important information within it. From both technical and business points of view, it is vital to ensure the security of data for the worldwide use of RFID technology, otherwise hacker or attacker can control the data transmission. So, to secure the RFID tag from ‘hacking’, a data security scheme for RFID tags based on programmable cellular automata has been proposed and implemented in this article. The processor for the system and the secret code generator have been designed in Very High Speed Integrated Circuit Hardware Description Language (VHDL) code using programmable cellular automata (PCA). The processor and ID generator have been simulated in Xilinx ISE 14.3 simulation tools and have implemented the design up to RTL schematic level and the processor has been emulated on the Kintex-7 FPGA board for verification in real environment.

Development and Evaluation of Vectorised and Multi-Core Event Reconstruction Algorithms within the CMS Software Framework

The processing of data acquired by the CMS detector at LHC is carried out with an object-oriented C++ software framework: CMSSW. With the increasing luminosity delivered by the LHC, the treatment of recorded data requires extraordinary large computing resources, also in terms of CPU usage. A possible solution to cope with this task is the exploitation of the features offered by the latest microprocessor architectures. Modern CPUs present several vector units, the capacity of which is growing steadily with the introduction of new processor generations. Moreover, an increasing number of cores per die is offered by the main vendors, even on consumer hardware. Most recent C++ compilers provide facilities to take advantage of such innovations, either by explicit statements in the programs sources or automatically adapting the generated machine instructions to the available hardware, without the need of modifying the existing code base. Programming techniques to implement reconstruction algorithms and optimised data structures are presented, that aim to scalable vectorization and parallelization of the calculations. One of their features is the usage of new language features of the C++11 standard. Portions of the CMSSW framework are illustrated which have been found to be especially profitable for the application of vectorization and multi-threading techniques. Specific utility components have been developed to help vectorization and parallelization. They can easily become part of a larger common library. To conclude, careful measurements are described, which show the execution speedups achieved via vectorised and multi-threaded code in the context of CMSSW.

실사기반 디지털 홀로그래픽 비디오의 실시간 생성을 위한 하드웨어의 설계

본 논문에서는 고속으로 홀로그램을 생성할 수 있는 하드웨어의 구조를 제안하고 이를 구현하였다. 제안한 하드웨어는 홀로그램 평면의 행 단위로 병렬 연산을 수행할 수 있는 구조를 가지고 있고, 한 행의 각 홀로그램 화소들이 독립적으로 연산될 수 있는 알고리즘을 이용하였다. 이러한 연산 방법을 통해서 홀로그램 생성 하드웨어서 가장 문제가 되는 메모리 접근량을 대폭 감소시킴으로써 하드웨어 처리능력의 실시간성을 대폭 향상시켰다. 제안한 하드웨어는 입력 인터페이스, 초기 파라미터 연산기, 홀로그램 화소 연산기, 라인 버퍼, 그리고 메모리 제어기로 구성된다. 제안한 하드웨어는 기존의 하드웨어와 동일한 처리능력을 가지면서도 메모리 접근횟수는 약 20,000배 감소시킬 수 있었다. 구현한 하드웨어는 198MHz에서 안정적으로 동작할 수 있었고, 168,960개의 LUT, 153,944개의 레지스터, 그리고 19,212개의 DSP 블록을 사용하였다.

Co-design of Compiler and Hardware Techniques to Reduce Program Code Size on a VLIW Processor


 
 
 Code size is a primary concern in the embedded computing community. Minimizing physical memory requirements reduces total system cost and improves performance and power efficiency. VLIW processors rely on the compiler to statically encode the ILP in the program before its execution, and because of this, code size is larger relative to other processors. In this paper we describe the co-design of compiler optimizations and processor architecture features that have progressively reduced code size across three generations of a VLIW processor.
 
 

Pushing the limits for medical image reconstruction on recent standard multicore processors

Volume reconstruction by backprojection is the computational bottleneck in many interventional clinical computed tomography (CT) applications. Today vendors in this field replace special purpose hardware accelerators with standard hardware such as multicore chips and GPGPUs. Medical imaging algorithms are on the verge of employing high-performance computing (HPC) technology, and are therefore an interesting new candidate for optimization. This paper presents low-level optimizations for the backprojection algorithm, guided by a thorough performance analysis on four generations of Intel multicore processors (Harpertown, Westmere, Westmere EX, and Sandy Bridge). We choose the RabbitCT benchmark, a standardized testcase well supported in industry, to ensure transparent and comparable results. Our aim is to provide not only the fastest possible implementation but also compare with performance models and hardware counter data in order to fully understand the results. We separate the influence of algorithmic optimizations, parallelization, SIMD vectorization, and microarchitectural issues and pinpoint problems with current SIMD instruction set extensions on standard CPUs (SSE, AVX). The use of assembly language is mandatory for best performance. Finally, we compare our results to the best GPGPU implementations available for this open competition benchmark.

The Collie

We describe the Collie collector, a fully concurrent compacting collector that uses transactional memory techniques to achieve wait-free compaction. The collector uses compaction as the primary means of reclaiming unused memory, and performs "individual object transplantations" as transactions. We introduce new terms and requirements useful for analyzing concurrent relocating collectors, including definitions of referrer sets, object transplantation and the notion of individually transplantable objects. The Collie collector builds on these terms and on a detailed analysis of an object's legal states during compaction. Collie uses a combination of read barriers, write barriers and transactional memory operations. Its read-barrier supports fast, direct object referencing while using a bound, constant time, wait- free triggering path. Collie thereby avoids the constant indirection cost of Brooks [9] style barriers or handle-based heaps [25]. Collie is demonstrated using speculative multi-address atomicity [11], a form of hardware transactional memory supported by the Azul Vega architecture [2]. We evaluate the Collie collector on the Azul platform, on which previous concurrent collectors such as the Pauseless Collector [12] and its generational variant [30] have been commercially available for several years. We discuss Collie's performance while running sustained workloads, and compare it to the Pauseless collector on the same platform. The Collie collector provides significant MMU [5] improvements even in the 1-msec time windows compared to the Pauseless collector. At the same time, it matches Pauseless in throughput and in the ability to scale to large heap sizes. We believe that the Collie collector is the first garbage collector to leverage hardware-assisted transactional memory. While Collie directly leverages Vega's speculative multi-address atomicity feature (SMA) [11], its design can be easily adapted to other hardware- assisted transactional memory systems. Specifically, the upcoming Intel TSX instruction set extensions [21] include capabilities similar to SMA. We expect Collie to be easily implementable on future commodity servers based on Intel Haswell processors and following processor generations.

Hybrid NOrec

Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such as Sun's prototype Rock processor and AMD's proposed Advanced Synchronization Facility (ASF), can efficiently execute many transactions, but abort in some cases due to various limitations. Hybrid TM systems can use a compatible software TM (STM) in such cases.

Efficient soft error protection for commodity embedded microprocessors using profile information

Successive generations of processors use smaller transistors in the quest to make more powerful computing systems. It has been previously studied that smaller transistors make processors more susceptible to soft errors (transient faults caused by high energy particle strikes). Such errors can result in unexpected behavior and incorrect results. With smaller and cheaper transistors becoming pervasive in mainstream computing, it is necessary to protect these devices against soft errors; an increasing rate of faults necessitates the protection of applications running on commodity processors against soft errors. The existing methods of protecting against such faults generally have high area or performance overheads and thus are not directly applicable in the embedded design space. In order to protect against soft errors, the detection of these errors is a necessary first step so that a recovery can be triggered. To solve the problem of detecting soft errors cheaply, we propose a profiling-based software-only application analysis and transformation solution. The goal is to develop a low cost solution which can be deployed for off-the-shelf embedded processors. The solution works by intelligently duplicating instructions that are likely to affect the program output, and comparing results between original and duplicated instructions. The intelligence of our solution is garnered through the use of control flow, memory dependence, and value profiling to understand and exploit the common-case behavior of applications. Our solution is able to achieve 92% fault coverage with a 20% instruction overhead. This represents a 41% lower performance overhead than the best prior approaches with approximately the same fault coverage.

Perceptual control of convolution based room simulators

Reverberation processing has been intensively studied in audio and acoustics research for many years now. Early approaches used feedback delay networks to control the temporal distribution of reflections and to simulate the statistical properties of room reverberation. Thanks to the increase in processing power and the development of low-latency convolution algorithms a new generation of reverberation processors has been developed. They apply room impulse responses (RIR) measured in real concert halls and thus guarantee naturalness and authenticity of reverberation. Extending this approach to the use of higher-order spherical microphone arrays provides the means for analyzing the spatiotemporal distribution of acoustic energy. This space-time-frequency representation of the acoustic wave field is also referred to as directional room impulse responses (DRIR) in literature. The objective of the presented work is to develop a perceptually motivated signal-processing environment based on the analysis and re-synthesis of DRIRs. It first extracts perceptual features from measured DRIRs (e.g. source presence and listener envelopment) and thus provides a perceptual signature of the measured room. The room acoustic behavior can then be modified along the various perceptual dimensions, preserving the microstructure of the original RIRs, before being re-synthesized for the use with reverberation processors.

Simplified VHDL Coding of Modified Non-Restoring Square Root Calculator

Square root calculation is one of the most useful and vital operation in digital signal processing which in recent generations of processors, the operation is performed by the hardware. The hardware implementation of the square root operation can be achieved by different means, but it is very dependent on programmer's sense and ability to write efficient hardware designs. This paper offers universal and shortest VHDL coding of modified non-restoring square root calculator. The main principle of the method is similar with conventional non-restoring algorithm, but it only uses subtract operation and append 01, while add operation and append 11 is not used. The strategy has conducted to implement successfully in FPGA hardware, and offer an efficient in hardware resource, and it is superior.

SERF and Modified SERF Adders for Ultra Low Power Design Techniques

The increasing demand for the high fidelity portable devices has laid emphasis on the development of low power and high performance systems. In the next generation processors, the low power design has to be incorporated into fundamental computation units, such as adders and multipliers. In this paper SERF and Modified SERF full adder topologies are presented. The analysis of Power, Delay, Power Delay Product (PDP) optimization characteristics of SERF Adder is designed. In order to achieve optimal power savings at smaller geometry sizes, proposed a heuristic approach known as Modified SERF adder model. The proposed Modified SERF adder model consumed the least power compare to SERF Adder with no deterioration in performance. Taken together, the results suggest that the Modified SERF Adder is well suited for ultra low power design and fast computation at smaller geometry sizes.

Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs

The new generation of multicore processors and reconfigurable hardware platforms provides a dramatic increase of the available parallelism and processing capabilities. However, one obstacle for exploiting all the promises of such platforms is deeply rooted in sequential thinking. The sequential programming model does not naturally expose potential parallelism that effectively permits to build parallel applications that can be efficiently mapped on different kind of platforms. A shift of paradigm is necessary at all levels of application development to yield portable and scalable implementations on the widest range of heterogeneous platforms. This paper presents a design flow for the hardware and software synthesis of heterogeneous systems allowing to automatically generate hardware and software components as well as appropriate interfaces, from a unique high‐level description of the application, based on the dataflow paradigm, running onto heterogeneous architectures composed by reconfigurable hardware units and multicore processors. Experimental results based on the implementation of several video coding algorithms onto heterogeneous platforms are also provided to show the effectiveness of the approach both in terms of portability and scalability.

FISH: Fast Instruction SyntHesis for Custom Processors

This paper presents Fast Instruction SyntHesis (FISH), a system that supports automatic generation of custom instruction processors from high-level application descriptions to enable fast design space exploration. FISH is based on novel methods for automatically adapting the instruction set to match an application in a high-level language such as C or C++. FISH identifies custom instruction candidates using two approaches: 1) by enumerating maximal convex subgraphs of application data flow graphs and 2) by integer linear programming (ILP). The experiments, involving ten multimedia and cryptography benchmarks, show that our contributed algorithms are the fastest among the state-of-the-art techniques. In most cases, enumeration takes only milliseconds to execute. The longest enumeration run-time observed is less than six seconds. ILP is usually slower than enumeration, but provides us with a complementary solution technique. Both enumeration and ILP allow the use of multiple different merit functions in the evaluation of data-flow subgraphs. The experiments demonstrate that, using only modest additional hardware resources, up to 30-fold performance improvement can be obtained with respect to a single-issue base processor.