Application Processor Research Articles

A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores

This paper presents power management and low power techniques of our heterogeneous quad/octa-core mobile application processor (AP). This AP has a combination of high-performance 2 GHz cores and energy-efficient 1 GHz cores. The maximum performance in the octa-core configuration is 35,600 DMIPS. The key design highlights are as follows. 1) Using a dedicated PLL and H-tree clock in the high-performance CPU achieves both 2 GHz operation and reduced dynamic power. 2) A low-leakage SRAM in a 28 nm HPM process is used and the leakage current of the peripheral circuits of the SRAM macro is optimized via multiple threshold voltages (Vt) and gate lengths (Lg), resulting in 24% leakage reduction of L1 cache. 3) The effects of process and voltage variations are accurately corrected by an on-chip process sensor and direct sensing of the voltage in the power mesh of the chip. 20% dynamic power reduction, 29% leakage power reduction and 40 mV improvement of minimum operation voltage are achieved. 4) An enhanced CPU clock control mechanism is employed, which uses an on-chip delay sensor to reduce AC voltage drop. 5) The heterogeneous CPU architecture maintains high performance even during thermal throttling.

A 1.22 TOPS and 1.52 mW/MHz Augmented Reality Multicore Processor With Neural Network NoC for HMD Applications

Real-time augmented reality (AR) is actively studied for the future user interface and experience in high-performance head-mounted display (HMD) systems. The small battery size and limited computing power of the current HMD, however, fail to implement the real-time markerless AR in the HMD. In this paper, we propose a real-time and low-power AR processor for advanced 3D-AR HMD applications. For the high throughput, the processor adopts task-level pipelined SIMD-PE clusters and a congestion-aware network-on-chip (NoC). Both of these two features exploit the high data-level parallelism (DLP) and task-level parallelism (TLP) with the pipelined multicore architecture. For the low power consumption, it employs a vocabulary forest accelerator and a mixed-mode support vector machine (SVM)-based DVFS control to reduce unnecessary external memory accesses and core activation. The proposed 4 mm × 8 mm HMD AR processor is fabricated using 65 nm CMOS technology for a battery-powered HMD platform with real-time AR operation. It consumes 381 mW average power and 778 mW peak power at 250 MHz operating frequency and 1.2 V supply voltage. It achieves 1.22 TOPS peak performance and 1.57 TOPS/W energy efficiency, which are, respectively, 3.58 × and 1.18 × higher than the state of the art.

Near-Threshold Energy- and Area-Efficient Reconfigurable DWPT/DWT Processor for Healthcare-Monitoring Applications

This brief presents an energy- and area-efficient discrete wavelet packet transform (DWPT) processor design for power-constrained and cost-sensitive healthcare-monitoring applications. This DWPT processor employs recursive memory-shared architecture to achieve low hardware complexity while performing required arbitrary-basis DWPT decomposition. By exploiting inherent characteristics of different physiological signals through an entropy statistic engine, the DWPT processor core can be reconfigured to compute multilevel wavelet decomposition with effective time and frequency resolution. Various design techniques from algorithm to circuit levels, including reconfigurable computing, lifting scheme, dual-port pipeline processing, near-threshold operation, and clock gating, are applied to achieve energy efficiency. With a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">$\mu\hbox{m}$</tex-math></inline-formula> CMOS technology at 0.5 V and 1 MHz, the DWPT core only consumes 26 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">$\mu\hbox{W}$</tex-math></inline-formula> for performing three-level 256-point DWPT decomposition with entropy statistic calculation. When integrated in an ARM Cortex-M0-based biomedical system-on-a-chip test platform, the DWPT processor achieves processing acceleration by three orders of magnitude and reduces energy consumption by four orders of magnitude compared with CPU-only implementations.

Embedded Web Server Application for Industrial Automation

Web Server based monitoring has been an issue for industries as they make use of PC-based servers which consume large power and occupy large area. This limitation can be overcome by replacing the existing PC-based server by an Embedded Web Server using Raspberry Pi. The prime objective of this paper is to design a remote data acquisition system which is controlled by Linux portable ARM processor and web server application with General Packet Radio Service (GPRS) technology. This system focuses not only on device monitoring but also controlling it. The monitoring and data collection is accompanied by a Short Message Service (SMS), an email alert which is initiated in order to avoid the occurrence of a critical event. The system is capable enough to withstand power failure and capable of restarting from the point of failure.

A Hybrid Scheme Based on Pipelining and Multitasking in Mobile Application Processors for Advanced Video Coding

One of the key requirements for mobile devices is to provide high-performance computing at lower power consumption. The processors used in these devices provide specific hardware resources to handle computationally intensive video processing and interactive graphical applications. Moreover, processors designed for low-power applications may introduce limitations on the availability and usage of resources, which present additional challenges to the system designers. Owing to the specific design of the JZ47x series of mobile application processors, a hybrid software-hardware implementation scheme for H.264/AVC encoder is proposed in this work. The proposed scheme distributes the encoding tasks among hardware and software modules. A series of optimization techniques are developed to speed up the memory access and data transferring among memories. Moreover, an efficient data reusage design is proposed for the deblock filter video processing unit to reduce the memory accesses. Furthermore, fine grained macroblock (MB) level parallelism is effectively exploited and a pipelined approach is proposed for efficient utilization of hardware processing cores. Finally, based on parallelism in the proposed design, encoding tasks are distributed between two processing cores. Experiments show that the hybrid encoder is 12 times faster than a highly optimized sequential encoder due to proposed techniques.

Research and Implementation on Networked Smart Sensor Based on IEEE1451 Standard

Firstly, the background and significance of IEEE1451 standard are introduced. Secondly, each protocol, especially the IEEE1451.2 standard of IEEE1451 family standards, is described respectively, including Smart Transducer Interface Module(STIM), Network Capable Application Processor (NCAP) and Transducer Electronic Data Sheet(TEDS). Then, a new design idea and implementation of a kind of networked smart sensor based on the IEEE451.2 is introduced in detail. Finally, the advantages and trends of the smart sensor based on IEEE1451 standard are summarized.

Algorithmic Based VLSI Architecture of Integrated Image Compression for CMOS Image Sensor

The challenging task of a CMOS image sensor is to have a well robust compression processor for multimedia and medical applications because it requires huge storage requirement of image data like small bowel images, retinal images and mammograms from different modalities such as ultra sonography, magnetic resonance imaging, computed tomography and media files. To overcome image degradation at high compression ratio (CR), we have proposed an integrated compression technique which combines quadrant tree decomposition (QTD) and lifting based discrete wavelet transform (DWT) to provide promising results with high compression at low bit rates without losing any information of the image and the advancement in technology such as backside illumination makes CMOS sensor to use in medical imaging application. The input image is undergone QTD coding followed by lifting based DWT. The quantised and encoded transform coefficients are then decoded using inverse lifting based DWT to obtain the reconstructed image. Simulation results of our proposed compression scheme gives 80 % pixel level memory reduction at a PSNR around 40 dB and less number of resources are utilized for different functions implemented in Xilinx ISE 9.1i varies from 0 to 53 % and it finds application in the field of e-health, tele-consultation, tele-radiology, tele-matics and telemedicine.

A High-Sensitivity Electric Probe Based on Board-Level Edge Plating and LC Resonance

A near-field probe fabricated on a printed circuit board (PCB) with a high sensitivity to electric fields is proposed. To achieve high sensitivity, board-level edge plating technology is employed to realize a copper patch replacing conventional pin-type electrodes. In addition, the sensitivity is further enhanced at a specific frequency band based on LC resonance. The proposed electric probe has been experimentally validated by near-field measurements on an application processor (AP) used in latest mobile phones with a sensitivity enhancement of around 20 dB in the Global Positional System (GPS) band compared to a commercial electric probe.

SmartCap

Power efficiency is increasingly critical to battery-powered smartphones. Given that the using experience is most valued by the user, we propose that the power optimization should directly respect the user experience. We conduct a statistical sample survey and study the correlation among the user experience, system runtime activities, and computational performance of an application processor. We find that there exists a minimal frequency requirement, called “saturated frequency”. Above this frequency, the device consumes more power but provides little improvements in user experience. This study motivates an intelligent self-adaptive scheme, SmartCap, that automatically identifies the most power-efficient state of the application processor. Compared to prior Linux power adaptation schemes, SmartCap can help save power from 11% to 84%, depending on applications, with little decline in user experience.

순환형 데이터 블록 체이닝을 이용한 차량용 블랙박스의 영상 데이터 무결성 보장 기법

The integrity assurance of recorded video by car black boxes are necessary as the car black box is becoming more popular. In this paper, we propose a video data integrity assurance scheme reflecting the features of car black box. The proposed method can detect any kind of deletion, insertion, modification of frames by cyclic chaining using inter block relation. And, it provides the integrity assurance function consistently even in cases of file overwriting because of no more free space in storage, partial file data lost. And non-repudiation is supported. Experimental results with a car black box embedded system with A8 application processor show that our method has a feasible computational overhead to process full HD resolution video at 30 frames per second in a real time.

Performance evaluation of plasma sprayed yttria coatings on high density graphite for cathode processor applications

Cathode processing in the pyrochemical reprocessing of spent metallic nuclear fuels encompasses melting and consolidation of uranium deposit obtained from the electro-refining step. Ceramic coated High density graphite (HDG) is considered for process crucibles in the cathode process. Thermal cycling behaviour of plasma sprayed yttria coated HDG discs with NiCrAlY bond coat was investigated at 1000 and 1100°C in vacuum. Each thermal cycle comprised soaking for 1h at the isothermal temperature followed by furnace cooling to ambient temperature. The microstructure and elemental composition of the as-received and thermal cycled yttria coated samples were analysed by scanning electron microscopy coupled with energy dispersive spectroscopy. Phase identification of the coating, performed by X-ray diffraction and laser Raman spectroscopic techniques confirmed the presence of only cubic phase in the as-received as well as thermal cycled samples. Yttria coating failed after 35 thermal cycles at 1000°C and 19 cycles at 1100°C. Micro-cracks developed after three uranium melting experiments at 1300°C could be owing to phase change in the bond coat.

Investigation of the Indirect Hypercube as Natural Architecture for Parallel Algorithms of a Transpose Type for FFT and Other Fourier-Related Transforms

Abstract The natural architectures are architectures, derived from the signal graph of the corresponding algorithm. That is why they are considered to be the most appropriate architectures for parallel realization of this algorithm. For Fast Fourier Transform algorithm (FFT) two types of natural architectures are known – the direct and the indirect hypercube. The direct hypercube has been investigated and analyzed a long time ago. The development of the concept of Indirect Hypercube, although quite old, is too difficult, controversal and still unfinished. Fast Hartley transform (FHT)/Real-valued Fast Fourier transform (RFFT) algorithms are important Fourier-related transforms, because they lower twice the operational and memory requirements when the input data is real-valued. These types of algorithms, however, have an irregular computational structure, which makes their parallel implementation a very difficult task. The aim of this paper is, based on the results achieved so far, to present further development of the concept Indirect Hypercube. A method of parametric synthesis of an indirect hypercube is described as a model of parallel FFT algorithms of a transpose type with different granularity/radix. This method is generalized for relevant RFFT/FHT and FCT algorithms. Two types of SIMD array architectures are described (radix-2 and radix-4), based on the indirect hypercube concept. These architectures are implemented as fast FFT/RFFT/FHT processors for real time applications. The performance estimation, as well as the estimation of resource utilization is carried out.

ULP-SRP

The latest biomedical applications require low energy consumption, high performance, and wide energy-performance scalability to adapt to various working environments. In this study, we present ULP-SRP, an energy-efficient reconfigurable processor for biomedical applications. ULP-SRP uses a Coarse-Grained Reconfigurable Array (CGRA) for high-performance data processing with low energy consumption. We adopted a compact-size CGRA and modified it to support dynamically switchable three performance modes with fine-grained power gating in order to further optimize the energy consumption. The energy-performance scalability is also accomplished with multiple performance modes and a Unified Memory Architecture (UMA). Experimental results show that ULP-SRP achieved 59% energy reduction compared to previous works. A technique of dynamic CGRA mode changing gives 18.9% energy reduction. ULP-SRP is a good candidate for future mobile healthcare devices.

A METHOD FOR STRUCTURAL SYNTHESIS OF NETWORK CAPABLE APPLICATION PROCESSORS

A method for structural synthesis of Network Capable Application Processors (NCAPs) is proposed. It is based on a method of morphological analysis and synthesis and includes phases of functional analysis, structural synthesis, and search for a set of optimal solutions. The proposed method combines lexicographical criterion of preference (L- criterion) at a stage of functional analysis and unconditional criterion of preference (Pareto optimality) during the search phase, which are considered in literature as alternative methods of search for optimal solutions. Combining of criteria, makes it possible to reduce the number of synthesized alternative variants at a stage of structural synthesis and all obtained solutions are allowable.

Energy Efficient Environment Monitoring System Based on the IEEE 802.15.4 Standard for Low Cost Requirements

Power consumption, portability, and system cost are important parameters in designing pervasive measurement systems. With these parameters in mind, wireless environment monitoring system with a capability to monitor greenhouse gases, such as CO, CO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , SO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> , NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> , O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> with environmental parameter is developed. In order to achieve the target design goals, the communication module, the wireless smart transducer interface module, and wireless network capable application processor module were developed based on the IEEE 802.15.4, IEEE 1451.2, and IEEE 1451.1 standards, respectively. The low cost and energy efficient gas sensing modules were successfully developed with improved tolerance to EMF/RFI noise. We defined recalibration of the system at time intervals to ensure that the desired accuracy is maintained. This paper presents the undertaken design detailing solutions to issues raised in previous research.

Silicon Process and Manufacturing Technology Evolution: An overview of advancements in chip making

silicon process technology is the dominant technology for the fabrication of a majority of the consumer electronics chips that are the building blocks of smartphones, tablets, microcontrollers, data converters, power management chips, and computers [1]. The functional block diagram of the silicon chips for a typical smartphone is shown in Figure 1: the applications processors, FLASH memory, power and battery management, touch-screen drivers, the 2G/3G/4G long-term evolution radio-frequency transceiver, the baseband modem, Wi-Fi, Bluetooth, GPS chips, audio CODEC, and CMOS image sensors, among others. The exception to this may be the power amplifier, which is still mainly fabricated by the gallium arsenide (GaAs) bipolar process as a niche area in the chip industry. Since the invention of the integrated circuit and the metal?oxide?semiconductor field-effect transistor (?MOSFET), the silicon process for making transistors and chips has become the driving force for the chip industry. The evolution of the cell phone and computers is intrinsically linked to the evolution of the silicon fabrication process advancement.

Fingerprint Pre-processing on ARM and DSP Platforms

In minutiae based fingerprint analysis, fingerprint image is pre-processed before extracting features. The pre-processing is carried out to obtain more accurate minutiae points. Implementing fingerprint programs on embedded systems can be considered as important especially for real time standalone applications. Reducing the pre-processing time is important for identification and verification in real time embedded systems. In this study, pre-processing of minutiae based fingerprint system is implemented on two different platforms: Texas Instruments Sitara AM3359 which is a single board computer and OMAP-L138 which is a development kit. OMAP-L138 is a low power application processor based on ARM9 and C674x DSP cores. AM3359 is microprocessor unit based on ARM Cortex-A8 core. Fingerprint pre-processing algorithms are implemented using C/C++ compiler and tested on three different cores: ARM9, DSP and ARM Cortex-A8. The execution times are compared with each other. The results show that using DSP core, execution time is substantially improved. DOI: http://dx.doi.org/10.5755/j01.eee.20.6.7287

Processor Tile Shapes and Interconnect Topologies for Dense On-Chip Networks

We propose two eight-neighbor, two five-nearest-neighbor, and three six-nearest-neighbor interconnection topologies for many-core processor arrays-three of which use five-sided or hexagonal processor tiles-which typically reduce application communication distance and result in an overall application processor that requires fewer cores and lower power consumption. A 16-bit processor with the appropriate number of input and output ports is implemented in all topologies and tile shapes. The hexagonal and five-sided processor tiles and arrays of tiles are laid out with industry standard automatic place and route design flow and Manhattan-style wires without full-custom layout. A 1080p H.264/AVC residual video encoder and a 54 Mb/s 802.11a/g OFDM wireless local area network baseband receiver are mapped onto all topologies. The six-neighbor hexagonal tile incurs a 2.9% area increase per tile compared with the four-neighbor 2-D mesh, but its much more effective interprocessor interconnect yields an average total application area reduction of 22% and an average application power savings of 17%.

OpenCL 및 Embedded GPU를 이용한 영상 특징 추출 및 파노라마 영상 생성의 병렬화

본 논문에서는 최신 embedded GPU를 사용하여 영상의 특징 추출 알고리즘(SIFT, SURF)을 병렬화하고, 특징 추출 및 정합 결과를 이용하여 파노라마 영상을 GPU에서 고속으로 생성하는 방법을 제안한다. 병렬화 된 알고리즘의 GPGPU(general purpose computation on GPU) 구현은 최신 스마트폰의 embedded GPU에서 지원하기 시작한 OpenCL을 이용하였다. 본 논문에서는 GPU에서 OpenGL Shading Language(GLSL)를 이용한 기존의 병렬화와 OpenCL을 이용한 새로운 병렬화 구현 결과를 효과적인 코드 구현 방법과 수행속도 관점에서 비교하였다. 실험결과, OpenCL은 GLSL과 유사한 수행 속도를 보였으며 embedded CPU와 비교하여 약 3~4배 빠른 수행속도를 보였다. 구현한 특징 추출 결과의 응용 사례로써, 특징 정합을 통한 영상 정합을 GPU상에서 병렬 수행하여 여러 장의 영상으로부터 파노라마 영상을 고속으로 생성하는 사례를 보인다. In this paper, we parallelize the popular feature detection algorithms, i.e. SIFT and SURF, and its application to fast panoramic image generation on the latest embedded GPU. Parallelized algorithms are implemented using recently developed OpenCL as the embedded GPGPU software platform. We compare the implementation efficiency and speed performance of conventional OpenGL Shading Language and OpenCL. Experimental result shows that implementation on OpenCL has comparable performance with GLSL. Compared with the performance on the embedded CPU in the same application processor, the embedded GPU runs 3~4 times faster. As an example of using feature extraction, panorama image synthesis is performed on embedded GPU by applying image matching using detected features.

IEEE 1451-Based Sensor Interfacing and Data Fusion for Fire Smoke Detection

The performance of a fire sensor has a significant effect on fire detection. Today’s fire alarm systems, such as smoke and heat sensors, however are generally limited to a close proximity to the fire; and cannot provide additional information about fire circumstances. Thus, it is essential to design a suite of low-cost networked sensors that provide the capability of performing distributed measurement and control in real time. In this work, a wireless sensor system was developed for fire detection. The purpose of this paper is to analyze the integration of traditional fire sensors into intelligent fire management systems by using the smart transducer concept. An automated video processing sensor for fire smoke monitoring applications is integrated into an surveillance network as a case study and supported sensor fusion assessment to improve the resistance to nuisance alarms. The proposed sensor system for fire detection was developed to reconcile issues related to proliferation and interoperability, and the architecture can support a smart transducer interface (IEEE 1451). The proposed embedded system for STIM (smart transducer interface module) and NCAP (network capable application processor) will be implemented with DSP. To realize the self-identification of transducers and plug-and-play connections, a transducer electronic data sheet (TEDS) is also stored inside the DSP. The acquired sensor data are pre-processed and applied to discriminate nuisance sources. The IEEE 1451 standard has been integrated into an automatic video-based fire smoke detection system. The proposed architecture has been tested on an experimental setup with the purpose of monitoring fire incidents successfully.