Processor Chip Research Articles

Simultaneous high-speed cutting and high-feed milling: An investigation on surface integrity

In this article, the potential of high-speed machining with an inverse cutting ratio b/h < 1 (uncut width of chip b to uncut chip thickness h) is presented based on the evaluation of surface integrity. If the machining is realized with a low cutting ratio many process quantities and chip formation mechanisms are fundamentally changed. As a result, the cutting process is stabilized through reduced feed forces and improved chip removal conditions. For the investigations, face-milling trials were carried out on an aluminum alloy (EN AC-42100) under conventional and high cutting speeds with variation of the feed per tooth and the use of cemented carbide and polycrystalline diamond tools. It is shown that when both machining strategies are combined, there is no further reduction in force components or improvement in surface topography. When the feed per tooth is increased at high cutting speeds, there is a linear increase in force components but surface roughness remain almost unchanged. After an initial increase in surface residual stresses, increasing the cutting speed leads mainly to compressive surface residual stresses. Overall, the surface integrity is influenced by the choice of cutting material and the micro-geometry of the cutting edge radius.

MorphBungee: A 65-nm 7.2-mm2 27-μJ/image Digital Edge Neuromorphic Chip with On-Chip 802-frame/s Multi-Layer Spiking Neural Network Learning.

This paper presents a digital edge neuromorphic spiking neural network (SNN) processor chip for a variety of edge intelligent cognitive applications. This processor allows high-speed, high-accuracy and fully on-chip spike-timing-based multi-layer SNN learning. It is characteristic of hierarchical multi-core architecture, event-driven processing paradigm, meta-crossbar for efficient spike communication, and hybrid and reconfigurable parallelism. A prototype chip occupying an active silicon area of 7.2 mm2 was fabricated using a 65-nm 1P9M CMOS process. when running a 256-256-256-256-200 4-layer fully-connected SNN on downscaled 16 × 16 MNIST images. it typically achieved a high-speed throughput of 802 and 2270 frames/s for on-chip learning and inference, respectively, with a relatively low power dissipation of around 61 mW at a 100 MHz clock rate under a 1.0V core power supply, Our on-chip learning results in comparably high visual recognition accuracies of 96.06%, 83.38%, 84.53%, 99.22% and 100% on the MNIST, Fashion-MNIST, ETH-80, Yale-10 and ORL-10 datasets, respectively. In addition, we have successfully applied our neuromorphic chip to demonstrate high-resolution satellite cloud image segmentation and non-visual tasks including olfactory classification and textural news categorization. These results indicate that our neuromorphic chip is suitable for various intelligent edge systems under restricted cost, energy and latency budgets while requiring in-situ self-adaptative learning capability.

Research Model Analysis of Muscle Power and Measuring Methods

Momentum is one of the most common sources of power for collecting. This article is important in the development of human power as it is a motivational investigation into the wood chipping process. An effective computational framework was established for the following variables: the power required to accelerate the spinning wheel, arterial pressure rise, and time needed for achieving spinning wheel speed. Five people with different physical characteristics pedaled. The energy production unit and output necessary for every individual are to be evaluated. The method of cycling and engaging the power transmitter can be considered a different subject of inquiry in this study. A separate experimental strategy was devised to measure human energy, and many factors were identified for further investigation for the first time, an effort was made to calculate the amount of human power necessary to operate any machine. The originality of the present study is regarded as of the utmost significance since it is transferable to any mathematical framework developed.

Environmental Assessment of Metal Chip Recycling – Quantification of Mechanical Processing's Global Warming Potential

Material recycling is an essential lever for improving the sustainability of production processes. One way of reusing metal chips that occur as waste in machining or other subtractive manufacturing processes is to mechanically pretreat and remelt them. In mechanical pretreatment, the chips are separated from the cutting fluid by a centrifuge and then briquetted directly on site. This simplifies the handling and makes the transport and subsequent remelting more efficient than in thermal processing alone. The main objective of this work is to quantitatively assess the environmental impacts of the described recycling process, focusing on the global warming potential. Furthermore, recycling by means of mechanical chip processing is compared with alternatives such as thermal drying and primary material extraction. A parametric life cycle assessment (LCA) model has been developed for this purpose. The model considers equipment, material, throughput and location variations to analyze different use cases. The results of the LCA of an exemplary use case show that environmental benefits result from a higher bulk density during transport and a lower energy input during remelting due to a lower liquid content.

Analysis of the Configuration for State-of-art AI Chips and Applications

As a matter of fact, the artificial intelligence chips provide core hardware computing support for the rapid development and application of artificial intelligence technology in recent years. In reality, they are the key driving force for the efficient, rapid application and energy-saving operation of artificial intelligence technology and are also the strategic commanding heights of the era of artificial intelligence. The purpose of this study is to analyze and summarize the architecture and practical application of the most advanced artificial intelligence chips. On this basis, this study will first analyze the development process of AI chips. At the same time, the classification, main architecture and working principle of AI chips are introduced. In addition, the study explains the application of AI chips in the existing mainstream market. Finally, this study will analyze the limitations of its research as well as look forward to the future. Overall, these results shed light on guiding further exploration of AI chips.

Analysis of the Principle and Configuration of AI Chip and the State-of-art Applications

AI chips are specialized hardware components designed to accelerate AI operations, making them crucial for various industries. This study provides a comprehensive overview of artificial intelligence (AI) chips, their structure, principles, fabrication process, applications, limitations, and future outlooks. The article discusses the components commonly found in AI chip structures, including processing units, memory hierarchy, interconnects, and specialized hardware units. It delves into the principles guiding AI chip design, such as specialization, parallelism, low precision arithmetic, and hardware-software co-design. The fabrication process of AI chips involves intricate steps, including design, mask generation, deposition, lithography, and testing. Applications of AI chips span data centers, edge computing, autonomous vehicles, healthcare, NLP, and more. Despite their advancements, AI chips have limitations, such as energy efficiency and specificity, but the future holds promise with improvements in energy efficiency, specialized acceleration, hybrid architectures, and quantum AI chips. Overall, AI chips have transformed the AI landscape, setting the stage for continued innovation and impact in various sectors.

Principle and Application of Biophotonic Chips

Contemporarily, biophotonic chips have garnered significant attention from researchers due to their strong immunity to electromagnetic interference, high sensitivity, rapid response rate, and relatively simple structural design. They have found extensive applications in fields such as medical diagnosis, food quality and safety testing, environmental monitoring, and national security. This article provides an overview of the development history, fundamental principles, applications, and fabrication processes of biophotonic chips. The earliest development of biophotonic chips can be traced back to the end of the 20th century. The basic principle involves the interaction of light, utilizing technologies like photonic crystals, surface plasmon resonance, and fluorescence spectroscopy to achieve the detection and analysis of biological molecules. The article briefly describes the fabrication process of biophotonic chips, which involves intricate techniques such as photolithography and electron beam exposure. Furthermore, it analyzes and discusses their widespread applications in medical diagnosis, drug development, and environmental monitoring, among other fields. Lastly, the study evaluates the key challenges present in biophotonic chips and provides an analysis of their future development prospects.

Analysis the Principle of AI Chip Principle and the State-of-art Applications

In recent years, AI chips are widely used in advance IC manufacturing. On this basis, this study provides an in-depth analysis of the principles and state-of-the-art applications of AI chips. This research first briefly introduces the history of artificial intelligence and the emergence of artificial intelligence chips as specialized hardware components aimed at effectively performing complex calculations required for artificial intelligence tasks. The article then delves into the basic definition and description of AI chips, the differences between AI chips and ordinary chips, the architecture and manufacturing process of AI chips, application scenarios and results, and the limitations of current AI chips. At the same time, the study also emphasizes the impact of artificial intelligence chips on the field of artificial intelligence research and their potential to shape the future of computing. Overall, the result of the study is a valuable resource for anyone interested in understanding the principles and applications of AI chips.

Source of IC power consumption and low power design

In these years, with the continuous development of 14nm and 7nm chip processes and the increasing popularity of computers, cell phones, and smart homes, the growing market of electronic products and ultra-fine research for the reliability of the chip requirements gradually increased. The method of reducing power consumption in the new context of new technology is called the chip field die-cut concern. This paper mainly summarizes two aspects of power consumption sources and methods to reduce power consumption, to provide a reference basis for future research directions: First, the major sources of power consumption are static power consumption and dynamic power consumption. The primary sources of static power consumption are sub-threshold leakage and gate leakage current. This paper also mentions some other leakage currents, such as reverse bias PN junction current and induced leakage current, which can be more carefully considered when exploring methods to reduce power consumption. A more comprehensive consideration when exploring ways to reduce power consumption. Dynamic power consumption is mainly divided into Switching power and Internal power and short-circuit power. Then we summarize the existing methods which can reduce power consumption: Clock gating (including Clock gating without a latch and Clock gating with a latch), Dynamic voltage and frequency scaling, multi-supply and multi-voltage technology, Power gating and multi-threshold voltage. These methods are from a proprietary perspective to reduce power consumption.

The Utilization of Pangas Catfish Fish Skin (Pangasius pangasius) in Making Skin Chips

Catfish is a popular freshwater fish and is in great demand as a consumption fish because catfish meat has a delicious taste and is quite high in calories and protein. Catfish skin as a by-product of fillet production can be used as raw material for processing chips. This research aims to determine the effect of soaking ingredients on the physical and chemical characteristics of catfish skin chips. This research was carried out by making catfish skin chips through the process of first washing, first soaking with soaking materials, second washing, second soaking in spices, drying, cutting, frying, and packed. The treatment in this research is the soaking material (in the first soaking) used. There were 4 treatments with different soaking ingredients, including: P0 (control), P1 (lime), P2 (acetic acid/vinegar), and P3 (palm vinegar). After the skin chips with the 4 treatments have been produced, quality testing is carried out on the product. Tests were carried out on yield, consumer acceptability through hedonic testing, physical characteristics of skin chips through analysis of crispness, efflorescence and oil absorption, chemical characteristics through proximate analysis, and microbial contamination through ALT analysis. Treatment P1 is known to have the highest yield, crispness, oil absorption capacity, and efflorescence ability among other treatments. Next, the products tested for chemical content are selected based on the treatment that obtains the highest level of consumer acceptance. Based on hedonic testing, it is known that P1 is the treatment most sought after by consumers. From the results of the chemical analysis that has been carried out, the ash content and protein content of fish skin chips in P1 is higher than P0, but has a lower water content than P0. The Total Plate Number (ALT) value for each catfish skin chips parameter exceeds the standard limit of SNI 7388:2009, namely 5x105 CFU/g.

Heterogeneous Integration of Chiplets, Lego-like IP for More than Moore

The semiconductor industry is facing an inflection point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic solutions, which are hitting or coming close to the limits of manufacturing and physics. This is driving an emerging trend to disaggregate what typically would be implemented as an SoC into solid, fabricated IP blocks, otherwise known as chiplets. These chiplets typically provide a specific function implemented in an optimal chip process node. Several chiplets and an optional, custom SOC device mounted and interconnected in a single packing using high speed/bandwidth interfaces that will then deliver monolithic or greater performance at a reduced cost, higher yield, and with only a slightly larger area as a heterogeneous integrated advanced package. As fabless semiconductor companies begin to bring these disaggregated chiplets to market, their successful adoption requires the fabless semiconductor industry to standardize on a set of interface protocols that will offer Lego-like plug and play compatibility between different suppliers chiplets creating a truly open ecosystem and supply chain. When it comes to the physical heterogeneous integration of these chiplets it is typically achieved using a high-performance silicon-like interposer substrate. Such substrates typically require silicon-like design rules and design techniques along with their own specific analysis and verification requirements. The supply chain for these substrates does not change significantly, it is still typically the leading semiconductor foundries and OSATs however the level of interaction, requirements, and signoff approvals does change bringing often new demands and challenges. Is this a revolution or an evolution, it depends on your starting point? Does it need an entirely new set of workflows and design tools? Can we evolve in some stepwise linear process from where we are today with monolithic or traditional system-in-package type designs into this next-generation design environment? This paper will explore these new challenges and outline 5 key workflows that address and manage them. These 5 workflows span interlinked domain areas starting with architecture definition before progressing to design that incorporates planning, prototyping, and technology co-optimization of the chosen architecture as well as the detailed physical implementation of substrates before moving to multi-physics analysis, device-level test, and then manufacturing. This paper will then recommend workflow adoption focus areas that we have seen provide immediate heterogeneous integration capability benefits while providing a managed methodology adoption and migration process that minimizes disruption, risk, and of course cost that can bring heterogeneous integration based chiplet design within reach of the mainstream instead of only being accessible to the mega iDMs and fabless semi’s.

Microwave wood chip treatment use in chemical pulp manufacturing (technical-economic assessment)

The low permeability of many wood species causes problems in the chemical pulp industry. These include very long cooking times, high chemical consumption, large material losses, high energy consumption, and environmental pollution. New microwave (MW) wood modification technology can provide an increase in wood permeability for liquids and gases that solves many of these problems. MW wood pre-treatment can increase pulp mill throughput, reduce chemical and power consumption, increase pulp quality and yield, and improve environmental performance. Economic modelling of this new technology use in different chemical pulp mill conditions allowed to assess the effect of capital costs, electricity costs, labour costs and other cost components to specific total costs of MW chip processing. MW chip treatment costs for pulp mills with output 50,000 to 500,000 ait dry ton (ADT) per year at electricity cost range US$0.04 to US$0.24/kWh vary in the range from US$17.7 to US$60.8 per air dry ton of pulp. Electricity costs form the most significant part – 51- 69% of the total specific costs of MW chip processing at electricity costs US$0.08 to US$0.12/kWh. New technology applications in different Russian conditions can provide benefits up to 7 – 22 Mil US$ per year for pulp mills with output of more than 200,000 ADT/year. The ecological effect and high economic advantages of this MW technology provide a good opportunity for commercialisation.

Optimized FIR Filter Using Genetic Algorithms: A Case Study of ECG Signals Filter Optimization

The advancement in technology and the availability of specialized digital signal processing chips have made digital filter design and implementation more feasible in a variety of fields, including biomedical engineering. This paper makes two key contributions. First, it uses a genetic algorithm to optimize the coefficients of finite impulse response (FIR) filters. Second, it conducts a case study on using genetic algorithms to optimize FIR filters for electrocardiogram (ECG) biomedical signal noise removal. The goal of the proposed filter design approach is to achieve the desired signal bandwidth while minimizing the side lobe level and eliminating unwanted signals using a genetic algorithm. The results of a comprehensive analysis show that the genetic algorithm-based filter is more effective than conventional filter designs in terms of noise removal efficiency.

Analog Convolutional Operator Circuit for Low-Power Mixed-Signal CNN Processing Chip

In this paper, we propose a compact and low-power mixed-signal approach to implementing convolutional operators that are often responsible for most of the chip area and power consumption of Convolutional Neural Network (CNN) processing chips. The convolutional operators consist of several multiply-and-accumulate (MAC) units. MAC units are the primary components that process convolutional layers and fully connected layers of CNN models. Analog implementation of MAC units opens a new paradigm for realizing low-power CNN processing chips, benefiting from less power and area consumption. The proposed mixed-signal convolutional operator comprises low-power binary-weighted current steering digital-to-analog conversion (DAC) circuits and accumulation capacitors. Compared with a conventional binary-weighted DAC, the proposed circuit benefits from optimum accuracy, smaller area, and lower power consumption due to its symmetric design. The proposed convolutional operator takes as input a set of 9-bit digital input feature data and weight parameters of the convolutional filter. It then calculates the convolutional filter’s result and accumulates the resulting voltage on capacitors. In addition, the convolutional operator employs a novel charge-sharing technique to process negative MAC results. We propose an analog max-pooling circuit that instantly selects the maximum input voltage. To demonstrate the performance of the proposed mixed-signal convolutional operator, we implemented a CNN processing chip consisting of 3 analog convolutional operators, with each operator processing a 3 × 3 kernel. This chip contains 27 MAC circuits, an analog max-pooling, and an analog-to-digital conversion (ADC) circuit. The mixed-signal CNN processing chip is implemented using a CMOS 55 nm process, which occupies a silicon area of 0.0559 mm2 and consumes an average power of 540.6 μW. The proposed mixed-signal CNN processing chip offers an area reduction of 84.21% and an energy reduction of 91.85% compared with a conventional digital CNN processing chip. Moreover, another CNN processing chip is implemented with more analog convolutional operators to demonstrate the operation and structure of an example convolutional layer of a CNN model. Therefore, the proposed analog convolutional operator can be adapted in various CNN models as an alternative to digital counterparts.

FPGA Implementation of Metaheuristic Optimization Algorithm

Metaheuristic algorithms are gaining popularity amongst researchers due to their ability to solve nonlinear optimization problems as well as the ability to be adapted to solve a variety of problems. There is a surge of novel metaheuristics proposed recently, however it is uncertain whether they are suitable for FPGA implementation. In addition, there exists a variety of design methodologies to implement metaheuristics upon FPGA which may improve the performance of the implementation. The project begins by researching and identifying metaheuristics which are suitable for FPGA implementation. The selected metaheuristic was the Simulated Kalman Filter (SKF) which proposed an algorithm that was low in complexity and used a small number of steps. Then the Discrete SKF was adapted from the original metaheuristic by rounding all floating-point values to integers as well as setting a fixed Kalman gain of 0.5. The Discrete SKF was then modeled using behavioral modeling to produce the Binary SKF which was then implemented onto FPGA. The design was made modular by producing separate modules that managed different parts of the metaheuristic and Parallel-In-Parallel-Out configuration of ports was also implemented. The Discrete SKF was then simulated on MATLAB meanwhile the Binary SKF was implemented onto FPGA and their performance were measured based on chip utilization, processing speed, and accuracy of results. The Binary SKF produced speed increment of up to 69 times faster than the Discrete SKF simulation.

Design and development of MTCA.4-based generic control and data acquisition module for CSNS-II and SAPS-TP

A new generation of domestically generic control and data acquisition AMC module has been developed to meet the requirements of the upgrade and renovation of the RCS LLRF system in the CSNS-II project, as well as the horizontal testing needs of the SAPS-TP. This module complies with the MicroTCA.4 standard and utilizes the Xilinx ZYNQ 7045 SOC as the core data processing chip. It can simultaneously run FPGA algorithms and the EPICS IOC remote control application program, serving as an autonomous control node. The module is equipped with 8 channels of 125 MSPS 16-bit ADC and 2 channels of 16-bit DAC with a maximum sampling rate of up to 500 MSPS. It also features standard expansion interface, front optical panel fiber interface, external clock interface, front panel digital IO interface, and more, catering to the needs of multiple systems in accelerator facilities such as radio-frequency, beam diagnostics, and control system. Additionally, the module can function independently for smaller-scale experimental and testing systems, such as the LLRF system for horizontal testing of SAPS-TP. To guarantee the seamless integration and proper operation of the AMC module within the MicroTCA.4 ecosystem, the MMC mezzanine card has been developed and thoroughly tested. In order to further reduce costs for small-scale systems, we optimized the software of the MMC so that the AMC board can run without the MCH module and realize self-health monitoring. For common applications, we have developed a complete software architecture and demo programs, including FPGA firmware, embedded Linux operating system, kernel driver modules, and EPICS IOC demo application programs. Detailed measurements have been conducted on hardware performance such as SNR, SFDR, channel isolation, as well as software performance including AXI DMA data bandwidth and system resources utilization, etc. The measurement results indicate that the module's performance indicators meet the design requirements.

III–V gain region/Si waveguide hybrid lasers by chip-on-wafer hydrophilic bonding process using UV-ozone treatment

The direct bonding process of InP chips on a silicon-on-insulator (SOI) wafer is investigated using surface hydrophilization by UV-ozone treatment. The influence of the treatment on surface roughness is observed by atomic force microscopy, and found to be negligibly small. A high-quality III–V/Si bonding interface without crystal defects is verified in a scanning transmission electron microscope observation. The III–V layers remaining on the SOI wafer after the removal process of the InP substrate show uniform photoluminescence intensity over the whole region of the chip, indicating a bonding interface without the influence of lateral etching and peeling-off. From this bonding process, Fabry–Perot lasers with III–V gain and Si waveguide regions are fabricated, and cw operation is successfully achieved at a stage temperature from 20 °C to 85 °C. Stable operation is also confirmed from the changes of threshold current in the aging test (200 mA at 85 °C) after 2000 h.

Die shear analyze of electrically conductive adhesives in GaN wafer application

Because of the demand for high-speed and broadband networks, 5G technology has paid much attention. On the one hand, due to the transit frequency of 5G, which is 450 MHz ~ 6GHz and 24 GHz ~ 52 GHz, the RF component has to deal with a higher frequency than previous communication. On the other hand, a massive high-power channel is required for some applications, like wireless communication base stations, military applications, satellite communication, and TV broadcasting. Therefore, GaN has become a good choice for high-power and high-frequency RF applications. In GaN RF chips, electrically conductive adhesive (ECA) is a key component that restricts heat, electrical conductivity, and reliability. This research studied two ECAs in the die attach process of a 5G base station RF amplifier chip, ABP 8068TA from LOCTITE Corporation and ASP 295-09P9 from Heraeus Group. During the research, ASP 295-09P9 has different die shear performance for GaN and GaAs die. After troubleshooting, operation error, such as the uneven spread of ECA and height of ECA, is excluded. By testing the wafer back surface, it is found that both GaN die and GaAs die back are pure Au, but GaAs die back's roughness is 0.049um, which is rougher than GaN's (0.032um). It is reasonable to assume that a smoother surface is a disadvantage for the necking mechanism.

Design and fabrication of cryogenic multiplexing control chip

This paper presents a design and fabrication process of a cryogenic multiplexing control chip (MCC) for superconducting quantum computers. The working temperature of MCC can be 10 ∼ 30 mK, because it could be integrated with quantum processor in the same package. With a multiplexing ratio of 1:4 and designed working frequency 4–8 GHz, the MCC is a non-reciprocity device which consisted of bandpass filters and isolators, which are based on tunable inductor bridges (TIB). The MCC chip size is 6 × 6 mm2 and includes λ/2 coplanar waveguides resonators, superconducting quantum interference device arrays, capacitors, low pass filters, baluns and bias lines. Adopting self-aligned process of Josephson junctions, the fabrication of MCC constitutes four lithography masks. The modular design of MCC could facilitate the development of large-scale superconducting quantum computers.

Youth Empowerment of St. Stefanus Holima (OMK) Catholic Church Through the Processing and Packaging of Sweet Potato Chips

Sweet potatoes in the Papuan Mountains region are very abundant and are sold without any processed variations. It is not uncommon for sweet potatoes to not sell even though the price is relatively cheap and affordable for all levels of society. For this reason, community service activities are carried out through community empowerment in implementing technology for processing and packaging sweet potato chips. The aim of this activity is to provide education to church youth (OMK) in Isakusa village to support increasing the income of church youth, and to support government programs in the agricultural sector. The method of implementing activities starts from determining the location, scheduling, socialization, making chips, and packaging the chips. The results of the training on processing and packaging sweet potato chips received a good response from the young people of St. Catholic Church (OMK). Stefanus Holima Wamena because during training it is not uncommon for the youth involved to show facial expressions that are curious, interested, happy and full of enthusiasm. Some of them said that they were very happy and satisfied with the products they had made and felt motivated to make them independently to sell to local people and local and foreign tourists as a form of home business that could increase their income. They also said that if possible, this kind of activity would be carried out sustainably by processing various types of basic materials which are superior in Wamena in particular and Mountain Papua in general.