Processor Allocation Research Articles

Using task migration to improve non-contiguous processor allocation in NoC-based CMPs

In this paper, a processor allocation mechanism for NoC-based chip multiprocessors is presented. Processor allocation is a well-known problem in parallel computer systems and aims to allocate the processing nodes of a multiprocessor to different tasks of an input application at run time. The proposed mechanism targets optimizing the on-chip communication power/latency and relies on two procedures: processor allocation and task migration. Allocation is done by a fast heuristic algorithm to allocate the free processors to the tasks of an incoming application when a new application begins execution. The task-migration algorithm is activated when some application completes execution and frees up the allocated resources. Task migration uses the recently deallocated processors and tries to rearrange the current tasks in order to find a better mapping for them. The proposed method can also capture the dynamic traffic pattern of the network and perform task migration based on the current communication demands of the tasks. Consequently, task migration adapts the task mapping to the current network status. We adopt a non-contiguous processor allocation strategy in which the tasks of the input application are allowed to be mapped onto disjoint regions (groups of processors) of the network. We then use virtual point-to-point circuits, a state-of-the-art fast on-chip connection designed for network-on-chips, to virtually connect the disjoint regions and make the communication latency/power closer to the values offered by contiguous allocation schemes. The experimental results show considerable improvement over existing allocation mechanisms.

A Divide and Conquer Strategy for Scaling Weather Simulations with Multiple Regions of Interest

Accurate and timely prediction of weather phenomena, such as hurricanes and flash floods, require high-fidelity compute intensive simulations of multiple finer regions of interest within a coarse simulation domain. Current weather applications execute these nested simulations sequentially using all the available processors, which is sub-optimal due to their sub-linear scalability. In this work, we present a strategy for parallel execution of multiple nested domain simulations based on partitioning the 2-D processor grid into disjoint rectangular regions associated with each domain. We propose a novel combination of performance prediction, processor allocation methods and topology-aware mapping of the regions on torus interconnects. Experiments on IBM Blue Gene systems using WRF show that the proposed strategies result in performance improvement of up to 33% with topology-oblivious mapping and up to additional 7% with topology-aware mapping over the default sequential strategy.

Architecture of the Monitor System in Ternary Optical Computer

The monitor system architecture in ternary optical computer (TOC) was discussed. There were some important modules, such as the client, network communication module (NCM), data preprocess module (DPM), operation-request scheduling module (ORSM), optical processor allocation module (OPAM) and the embedded system in the architecture. And the communication protocols between these modules were analyzed and designed. At the same time, the functions of the modules were introduced.

An Improved Adaptive Space-Sharing Scheduling Policy for Non-dedicated Heterogeneous Cluster Systems

Adaptive space-sharing scheduling algorithms tend to improve the performance of clusters by allocating processors to jobs based on the current system load. The focus of existing adaptive algorithms is on dedicated homogeneous and heterogeneous clusters. However commodity clusters are naturally non-dedicated and tend to be heterogeneous over the time as cluster hardware is usually upgraded and new fast machines are also added to improve cluster performance. The existing adaptive policies for dedicated cluster systems are not suitable for such conditions. Moreover existing adaptive policies use First-come-first-serve (FCFS) which is known to be sensitive of variance in service demand, as a job-selection policy for processor allocation. FCFS allocation of processors to jobs results in a situation where small jobs could be blocked by an earlier arrived large job. This paper fills these gaps by designing an efficient adaptive space-sharing scheduling algorithm for non-dedicated heterogeneous cluster systems. Evaluation results show that the proposed algorithm provide substantial improvement over existing algorithms at moderate to high system utilizations.

Supporting non-contiguous processor allocation in mesh-based chip multiprocessors using virtual point-to-point links

In this study, the authors propose a processor allocation mechanism for run-time assignment of a set of communicating tasks of input applications onto the processing nodes of a chip multiprocessor, when the arrival order and execution lifetime of the input applications are not known a priori. This mechanism targets the on-chip communication and aims to reduce the power and latency of the network-on-chip employed as the communication infrastructure. In this work, the authors benefit from the advantages of non-contiguous processor allocation mechanisms, by allowing the tasks of the input application mapped onto disjoint regions (submeshes) and then virtually connecting them by bypassing the router pipeline stages of the inter-region routers. Among different existing contiguous and non-contiguous processor allocation techniques, the authors have chosen and implemented four efficient schemes for the comparison purpose: the best fit and stack-based allocation algorithms as contiguous techniques and the greedy-available-busy-list algorithm and run-time incremental mapping as non-contiguous techniques. Experimental results show considerable improvements over all selected contiguous and non-contiguous methods.

Minimal Task Allocation in Multiprocessors using improved next-fit for RM scheduling

processor allocation in multiprocessors can be accomplished efficiently for reducing the required number of processors for the given task set, accounting reduced power consumption with maximum processor utilization. This work is based on next fit algorithm using Rate Monotonic Algorithm (RMA) for a fixed priority system. The work proposes a minimal task allocation algorithm for multiprocessor environment. The proposed method reduces the number of processors required for a given task set using improved next fit algorithm and the same has been evaluated and tested. The proposed algorithm gives better results when there is large number of tasks in the system.

User-defined schedulers for real-time concurrent objects

Scheduling concerns the allocation of processors to processes, and is traditionally associated with low-level tasks in operating systems and embedded devices. However, modern software applications with soft real-time requirements need to control application-level performance. High-level scheduling control at the application level may complement general purpose OS level scheduling to fine-tune performance of a specific application, by allowing the application to adapt to changes in client traffic on the one hand and to low-level scheduling on the other hand. This paper presents an approach to express and analyze application-specific scheduling decisions during the software design stage. For this purpose, we integrate support for application-level scheduling control in a high-level object-oriented modeling language, Real-Time ABS, in which executable specifications of method calls are given deadlines and real-time computational constraints. In Real-Time ABS, flexible application-specific schedulers may be specified by the user, i.e., developer, at the abstraction level of the high-level modeling language itself and associated with concurrent objects at creation time. Tool support for Real-Time ABS is based on an abstract interpreter that supports simulations and measurements of systems at the design stage.

Location of Processor Allocator and Job Scheduler and Its Impact on CMP Performance

Location of Processor Allocator and Job Scheduler and Its Impact on CMP PerformanceHigh Performance Computing (HPC) architectures are being developed continually with an aim of achieving exascale capability by 2020. Processors that are being developed and used as nodes in HPC systems are Chip Multiprocessors (CMPs) with a number of cores. In this paper, we continue our effort towards a better processor allocation process. The Processor Allocator (PA) and Job Scheduler (JS) proposed and implemented in our previous works are explored in the context of its best location on the chip. We propose a system, where all locations on a chip can be analyzed, considering energy used by Network-on-Chip (NoC), PA and JS, and processing elements. We present energy models for the researched CMP components, mathematical model of the system, and experimentation system. Based on experimental results, proper placement of PA and JS on a chip can provide up to 45% NoC energy savings.

Performance implications of non-uniform VCPU-PCPU mapping in virtualization environment

Virtualization technology promises to provide better isolation and consolidation in traditional servers. However, with VMM (virtual machine monitor) layer getting involved, virtualization system changes the architecture of traditional software stack, bringing about limitations in resource allocating. The non-uniform VCPU (virtual CPU)-PCPU (physical CPU) mapping, deriving from both the configuration or the deployment of virtual machines and the dynamic runtime feature of applications, causes the different percentage of processor allocation in the same physical machine,and the VCPUs mapped these PCPUs will gain asymmetric performance. The guest OS, however, is agnostic to the non-uniformity. With assumption that all VCPUs have the same performance, it can carry out sub-optimal policies when allocating virtual resource for applications. Likewise, application runtime system can also make the same mistakes. Our focus in this paper is to understand the performance implications of the non-uniform VCPU-PCPU mapping in a virtualization system. Based on real measurements of a virtualization system with state of art multi-core processors running different commercial and emerging applications, we demonstrate that the presence of the non-uniform mapping has negative impacts on application's performance predictability. This study aims to provide timely and practical insights on the problem of non-uniform VCPU mapping, when virtual machines being deployed and configured, in emerging cloud.

Large improvements in application throughput of long‐running multi‐component applications using batch grids

SUMMARYComputational grids with multiple batch systems (batch grids) can be powerful infrastructures for executing long‐running multi‐component parallel applications. In this paper, we evaluate the potential improvements in throughput of long‐running multi‐component applications when the different components of the applications are executed on multiple batch systems of batch grids. We compare the multiple batch executions with executions of the components on a single batch system without increasing the number of processors used for executions. We perform our analysis with a foremost long‐running multi‐component application for climate modeling, the Community Climate System Model (CCSM). We have built a robust simulator that models the characteristics of both the multi‐component application and the batch systems. By conducting large number of simulations with different workload characteristics and queuing policies of the systems, processor allocations to components of the application, distributions of the components to the batch systems and inter‐cluster bandwidths, we show that multiple batch executions lead to 55% average increase in throughput over single batch executions for long‐running CCSM. We also conducted real experiments with a practical middleware infrastructure and showed that multi‐site executions lead to effective utilization of batch systems for executions of CCSM and give higher simulation throughput than single‐site executions. Copyright © 2011 John Wiley & Sons, Ltd.

On the performance of non-contiguous allocation for common communication patterns in 2D mesh-connected multicomputers

The communication pattern used by applications can have a major influence on the performance of non-contiguous processor allocation in multicomputers. In this paper, the performance of well-known non-contiguous allocation strategies for 2D mesh multicomputers is re-visited considering several important communication patterns. These are the Near Neighbour, Ring, Divide and Conquer Binomial Tree (DQBT), Fast Fourier Transform (FFT), and Random communication patterns. The allocation strategies investigated are the Greedy Available Busy List (GABL), Multiple Buddy Strategy (MBS), Adaptive Non-contiguous Allocation (ANCA), and Paging(0). They are compared using detailed flit-level simulations. The results show that GABL is overall superior to the remaining non-contiguous allocation strategies. It produces superior average turnaround times and mean system utilization.

Optimized composition of performance‐aware parallel components

SUMMARYWe describe the principles of a novel framework for performance‐aware composition of sequential and explicitly parallel software components with implementation variants. Automatic composition results in a table‐driven implementation that, for each parallel call of a performance‐aware component, looks up the expected best implementation variant, processor allocation and schedule given the current problem, and processor group sizes. The dispatch tables are computed off‐line at component deployment time by an interleaved dynamic programming algorithm from time‐prediction meta‐code provided by the component supplier. Copyright © 2011 John Wiley & Sons, Ltd.

Statistical Modeling and Evaluation of Parallel Spacesharing Job Scheduling Algorithms for PCcluster using Design of Experiments 'DOE'

space-sharing job scheduling algorithms play an indispensible role in efficient allocation of processors of PC-cluster to the competing jobs to achieve one of the performance objective(s) viz. minimized mean response time (MRT), minimized average bounded slowdown or maximized throughput. Traditional performance modeling and evaluation studies of parallel space- sharing job scheduling algorithms are incompetent of predicting the combined or interaction effect on the response resulting due to simultaneous variation of two process variables. Present work is undertaken to predict and quantize the influence of main and interaction effects of the input scheduling process variables on the output MRT values using statistical approach of design of experiments (DOE). DOE based Response surface methodology (RSM) oriented experimental design is chosen to evaluate MRT values for two scheduling algorithms namely First Come First Serve (FCFS) and Fit Processors First Served (FPFS). Two empirical interaction models are suggested for both scheduling algorithms that predict MRT on the basis of multiple regression equations involving main and interaction effect terms of scheduling process variables. High value of adjusted coefficient of determination R 2 and insignificant lack of fit represent the goodness of fit of both the models to accurately predict the MRT values. Both the empirical interaction models are validated against additional experimental results. The comparative performance evaluation study on the basis of MRT reveals that the FPFS algorithm tends to outweigh the traditional FCFS policy.

Comparative Evaluation of RequestPartitioningbased Processor Allocation Strategies in 2D Meshbased Multicomputers

Partitioning-Based (RPB) allocation schemes remedy the problem of fragmentation by allowing parallel requests to be allocated non-contiguously in case contiguous allocation fails. Two RPB allocation schemes are proposed in literature; the Adaptive Non-Contiguous Allocation (ANCA) and the Bounded-Gradual-Partitioning (BGP) allocation. In ANCA, the frame requested by the parallel job is subdivided into two subframes of equal sizes at the longest dimension of the request. In BGP, requests are gradually partitioned into one large and another small subframe of multicomputers. In this paper, ANCA and BGP based allocation strategies are comparatively evaluated through exhaustive simulation-based experiments. Our experimental results also showed that the ANCA scheme can sustain higher system and communication loads compared to BGP in terms of major system performance metrics. We also observed that, in the BGP approach, increasing the partitioning bound value can slightly improve the performance of the parallel system. Comparatively, increasing the partitioning bound in the ANCA approach could significantly improve the performance of the parallel system.

A Modified and Efficient Algorithm for Static Task Assignment in Distributed Processing Environment

The Distributed Processing Environment [DPE] in which services provided for the network reside at multiple sites. Instead of single large machine being responsible for all aspects of process, each separate processor handles subset. In the distributed environments the program or tasks are also often developed with the subsets of independent units under various environments. The Allocation problems in any computer system play the key role for deciding the performance of the system. The allocation put the direct impact of software resources as well as hardware resources. In DPE, partitioning of the application software in to module and the proper allocation of these modules dissimilar processors are important factors, which determine the efficient utilization of resources. The static model discussed in this paper provide an optimal solution for assigning a set of “m” modules of a task to a set of “n” processors where m > n in a distributed system for evaluation for optimal time of the system.

Energy characteristic of a processor allocator and a network-on-chip

Energy characteristic of a processor allocator and a network-on-chip Energy consumption in a Chip MultiProcessor (CMP) is one of the most important costs. It is related to design aspects such as thermal and power constrains. Besides efficient on-chip processing elements, a well-designed Processor Allocator (PA) and a Network-on-Chip (NoC) are also important factors in the energy budget of novel CMPs. In this paper, the authors propose an energy model for NoCs with 2D-mesh and 2D-torus topologies. All important NoC architectures are described and discussed. Energy estimation is presented for PAs. The estimation is based on synthesis results for PAs targeting FPGA. The PAs are driven by allocation algorithms that are studied as well. The proposed energy model is employed in a simulation environment, where exhaustive experiments are performed. Simulation results show that a PA with an IFF allocation algorithm for mesh systems and a torus-based NoC with express-virtual-channel flow control are very energy efficient. Combination of these two solutions is a clear choice for modern CMPs.

Processor Allocation with Reduced Internal and External Fragmentation in 2D Mesh-based Multicomputers

Processor Allocation with Reduced Internal and External Fragmentation in 2D Mesh-based Multicomputers

Joint congestion control and processor allocation for task scheduling in grid over OBS networks

This paper presents a task scheduling algorithm that fulfills the coordination of congestion control in conjunction with processor allocation in the grid over optical burst switching networks. Two requirement criteria, namely deadline and payment, are considered and formulated as a user utility maximization function. The optimization problem is decomposed into two parts: congestion control for network transmission rate adjustment and processor allocation for computational capacity adjustment. The parameters from the resource layer are abstracted and provided to a cross-layer optimizer to maximize user’s utility function. The effectiveness and performance of the algorithm are evaluated via simulations. Comparison with other algorithms shows the efficiency of the proposed algorithm.

Fast and efficient processor allocation algorithm for torus-based chip multiprocessors

Processor Allocator (PA) is a crucial factor in modern Chip MultiProcessors (CMPs). A modern CMP uses Network on Chip (NoC) as communication technique between cores. Thus, the topology of the implemented NoC has also significant impact on the CMP’s performance. A good processor allocation technique needs to be fast and ensure the highest possible system utilization. In this paper, we propose a processor allocation technique for such an efficient and fast PA. The PA is driven by a Bit Map Allocation for Torus (BMAT) algorithm, which is a technique designed for k-ary 2-cube topology. The proposed BMAT scheme is presented and described along with a new Busy List Allocation for Torus (BLAT), Sorting Allocation for Torus (SAT) and Stack Based Allocation for Torus (SBAT) algorithms. The presented techniques are compared with previously known important schemes for k-ary 2-mesh topology. The research ideas have been verified using experiments that have also been described in the paper. The presented simulation results reveal that the proposed processor allocation algorithm for k-ary 2-cube, as a technique for PA, achieves better allocation time than all other existing algorithms while the CMP with such a PA is characterized by very high system utilization.

Improving grid performance through processor allocation considering both speed heterogeneity and resource fragmentation

Grid performance are usually measured by the average turnaround time of all jobs in the system. A job's turnaround time consists of two parts: queue waiting time and actual execution time, which in a heterogeneous grid environment, are severely affected by the resource fragmentation and speed heterogeneity factors. Most existing processor allocation methods focus on one of these two factors only. This paper proposes processor allocation methods, which consider both resource fragmentation and speed heterogeneity, to improve system performance of heterogeneous grids. Extensive simulation studies have been conducted to show that the proposed methods can effectively deliver better performance under most resource and workload conditions.