Processor Allocation Research Articles

Evaluation Scheme for NoC-based CMP with Integrated Processor Management System

Evaluation Scheme for NoC-based CMP with Integrated Processor Management SystemWith the opportunities and benefits offered by Chip Multiprocessors (CMPs), there are many challenges that need to be addressed in order to exploit the full potential of CMPs. Such aspects as parallel programs, interconnection design, cache arrangement and on-chip cores allocation become a limiting factor. To ensure validity of approaches and research, we propose an evaluation system for CMPs with Network-on-Chip (NoC) and processor management system integrated on one die. The suggested experimentation system is described in details. The proposed system that is used for tests and results of the experiments are presented and discussed. As decision making criteria, we consider energy efficiency of Processor Allocator (PA) and NoC, as well as NoC traffic characteristic (load balance). In order to improve the system understanding, brief overview on most important NoC and PA architectures is also presented. Analyzed results reveal that CMP with a PA controlled by IFF allocation algorithm for mesh systems and torus-based NoC driven by DORLB routing with express-virtual-channel flow control achieved the best traffic balance and energy characteristic.

On the Benefit of Processor Coallocation in Multicluster Grid Systems

In multicluster grid systems, parallel applications may benefit from processor coallocation, that is, the simultaneous allocation of processors in multiple clusters. Although coallocation allows the allocation of more processors than available in a single cluster, it may severely increase the execution time of applications due to the relatively slow wide-area communication. The aim of this paper is to investigate the benefit of coallocation in multicluster grid systems, despite this drawback. To this end, we have conducted experiments in a real multicluster grid environment, as well as in a simulated environment, and we evaluate the performance of coallocation for various applications that range from computation-intensive to communication-intensive and for various system load settings. In addition, we compare the performance of scheduling policies that are specifically designed for coallocation. We demonstrate that considering latency in the resource selection phase improves the performance of coallocation, especially for communication-intensive parallel applications.

Task migration in three-dimensional meshes

As a result of the emerging use of mesh-based multicomputers (and recently mesh-based multiprocessor systems-on-chip), issues related to processor management have attracted much attention. In a mesh-based multiprocessor, after repeated submesh allocations and de-allocations, the system network may be fragmented, i.e. there might be unallocated nodes in the network. As a result, in a system with contiguous processor allocation, no new tasks can start running due to the lack of enough free adjacent processors to form a suitable submesh. Although there might be enough free processors available, they remain idle until the allocator can find a set of adjacent free nodes forming a submesh to be used for the new task. This can lead to low system performance. Task migration was introduced as a solution to this problem through migration of tasks running on some submeshes to other free areas in order to reduce fragmentation by chaining the newly freed areas and disengaging nodes to form larger submeshes. In this paper, we propose a novel structured and formulated way to code task migration, which is helpful for congestion detection in different steps of task migration algorithms. Moreover, considering the fact that the 3D mesh-based multicomputers are now very popular, a new task migration algorithm in 3D meshes is proposed. We also address the special case of the 2D migration in a 3D mesh multicomputer.

Energy efficient scheduling of parallel tasks on multiprocessor computers

In this paper, scheduling parallel tasks on multiprocessor computers with dynamically variable voltage and speed are addressed as combinatorial optimization problems. Two problems are defined, namely, minimizing schedule length with energy consumption constraint and minimizing energy consumption with schedule length constraint. The first problem has applications in general multiprocessor and multicore processor computing systems where energy consumption is an important concern and in mobile computers where energy conservation is a main concern. The second problem has applications in real-time multiprocessing systems and environments where timing constraint is a major requirement. Our scheduling problems are defined such that the energy-delay product is optimized by fixing one factor and minimizing the other. It is noticed that power-aware scheduling of parallel tasks has rarely been discussed before. Our investigation in this paper makes some initial attempt to energy-efficient scheduling of parallel tasks on multiprocessor computers with dynamic voltage and speed. Our scheduling problems contain three nontrivial subproblems, namely, system partitioning, task scheduling, and power supplying. Each subproblem should be solved efficiently, so that heuristic algorithms with overall good performance can be developed. The above decomposition of our optimization problems into three subproblems makes design and analysis of heuristic algorithms tractable. A unique feature of our work is to compare the performance of our algorithms with optimal solutions analytically and validate our results experimentally, not to compare the performance of heuristic algorithms among themselves only experimentally. The harmonic system partitioning and processor allocation scheme is used, which divides a multiprocessor computer into clusters of equal sizes and schedules tasks of similar sizes together to increase processor utilization. A three-level energy/time/power allocation scheme is adopted for a given schedule, such that the schedule length is minimized by consuming given amount of energy or the energy consumed is minimized without missing a given deadline. The performance of our heuristic algorithms is analyzed, and accurate performance bounds are derived. Simulation data which validate our analytical results are also presented. It is found that our analytical results provide very accurate estimation of the expected normalized schedule length and the expected normalized energy consumption and that our heuristic algorithms are able to produce solutions very close to optimum.

Task Scheduling for Multiprocessor Systems with Autonomous Performance-Optimizing Control

In all non-blocking non-preemptive (NBNP) scheduling techniques for a multicomputer system for processor allocation, Largest-Job-First (LJF) technique proves to possess a unique characteristic in utilizing as many processors as possible compared to others such as First-Come-First-Serve (FCFS) and Smallest-Job-First (SJF). However, a job-bypass limit that is preset to preclude the starvation problem in an NBNP platform may lead to problems in all techniques. The scheduling becomes ”mandatory blocking” whenever a job reaches this bypass limit and thus has to be scheduled for allocation in the next immediate turn. This deprives the scheduling process the flexibility benefit in its non-blocking nature. Such an adverse effect is especially pronounced in LJF compared to the normally used FCFS one. Thus, how to find a balance in real time between employing the LJF and the FCFS in different situations is the main focus of this paper. We first propose an automatic control process which allows automatic adjustment on the algorithm based on the observed performance. This process, unlike the well-known feedback-control process, adjusts the algorithm based on an unbiased approach in order to disengage the dependence of performance on the input. We then propose two different scheduling techniques that simply employ this control process to self-adjust the weights in between using the two different techniques in real time. Performance results observed from our simulation runs show a significant improvement over the plain LJF and FCFS.

Mechanism of Resource Virtualization in RCS for Multitask Stream Applications

Virtualization of logic, routing, and communication resources in recent FPGA devices can provide a dramatic improvement in cost-efficiency for reconfigurable computing systems (RCSs). The presented work is “proof-of-concept” research for the virtualization of the above resources in partially reconfigurable FPGA devices with a tile-based architecture. The following aspects have been investigated, prototyped, tested, and analyzed: (i) platform architecture for hardware support of the dynamic allocation of Application Specific Virtual Processors (ASVPs), (ii) mechanisms for run-time on-chip ASVP assembling using virtual hardware Components (VHCs) as building blocks, and (iii) mechanisms for dynamic on-chip relocation of VHCs to predetermined slots in the target FPGA. All the above mechanisms and procedures have been implemented and tested on a prototype platform—MARS (multitask adaptive reconfigurable system) using a Xilinx Virtex-4 FPGA. The on-chip communication infrastructure has been developed and investigated in detail, and its timing and hardware overhead were analyzed. It was determined that component relocation can be done without affecting the ASVP pipeline cycle time and throughput. The hardware overhead was estimated as relatively small compared to the gain of other performance parameters. Finally, industrial applications associated with next generation space-borne platforms are discussed, where the proposed approach can be beneficial.

Rule-based automatic software performance diagnosis and improvement

There are many advantages to analyzing performance at the design level, rather than waiting until system testing. However the necessary expertise in making and interpreting performance models may not be available, and the time for the analysis may be prohibitive. This work addresses both these difficulties through automation. Starting from an annotated specification in UML, it is possible to automatically derive a performance model. This work goes further to automate the performance analysis, and to explore design changes using diagnostic and design-change rules. The rules generate improved performance models which can be transformed back to an improved design. They untangle the effects of the system configuration (such as the allocation of processors) from limitations of the design, and they recommend both configuration and design improvements. This paper describes a prototype called Performance Booster (PB), which incorporates several rules, and demonstrates its feasibility by applying PB to the design of several case studies (tutorial and industrial). It also addresses how the changes at the level of a performance model should be implemented in the software.

Hardware implementation of processor allocation schemes for mesh-based chip multiprocessors

Well-designed Processor Allocator (PA) is an important factor in modern Chip MultiProcessors (CMPs). It needs to be fast as well as area and energy efficient, because it is only a small component of the CMP. In this paper, we propose an architecture for such an efficient and fast PA. The PA structure is based on bit map approach and is driven by an Improved First Fit (IFF) algorithm, which is presented and described. Together with the proposed IFF technique, a new Improved Adaptive Scan (IAS) and an Improved Quick Allocation (IQA) algorithms are introduced and discussed and compared with previously known important techniques. The presented synthesis results reveal that the proposed PA achieves good frequency results while, at the same time is characterized by low logic utilization.

An Integrated Approach to Locality-Conscious Processor Allocation and Scheduling of Mixed-Parallel Applications

Complex parallel applications can often be modeled as directed acyclic graphs of coarse-grained application tasks with dependences. These applications exhibit both task and data parallelism, and combining these two (also called mixed parallelism) has been shown to be an effective model for their execution. In this paper, we present an algorithm to compute the appropriate mix of task and data parallelism required to minimize the parallel completion time (makespan) of these applications. In other words, our algorithm determines the set of tasks that should be run concurrently and the number of processors to be allocated to each task. The processor allocation and scheduling decisions are made in an integrated manner and are based on several factors such as the structure of the task graph, the runtime estimates and scalability characteristics of the tasks, and the intertask data communication volumes. A locality-conscious scheduling strategy is used to improve intertask data reuse. Evaluation through simulations and actual executions of task graphs derived from real applications and synthetic graphs shows that our algorithm consistently generates schedules with a lower makespan as compared to Critical Path Reduction (CPR) and Critical Path and Allocation (CPA), two previously proposed scheduling algorithms. Our algorithm also produces schedules that have a lower makespan than pure task- and data-parallel schedules. For task graphs with known optimal schedules or lower bounds on the makespan, our algorithm generates schedules that are closer to the optima than other scheduling approaches.

Rule-based automatic software performance diagnosis and improvement

There are many advantages to analyzing performance at the design level, rather than waiting until system testing. However the necessary expertise in making and interpreting performance models may not be available, and the time for the analysis may be prohibitive. This work addresses both these difficulties through automation. Starting from an annotated specification in UML, it is possible to automatically derive a performance model. This work goes further to automate the performance analysis, and to explore design changes using diagnostic and design-change rules. The rules generate improved performance models which can be transformed back to an improved design. They untangle the effects of the system configuration (such as the allocation of processors) from limitations of the design, and they recommend both configuration and design improvements. This paper describes a prototype called Performance Booster (PB), which incorporates several rules, and demonstrates its feasibility by applying PB to the design of several case studies (tutorial and industrial). It also addresses how the changes at the level of a performance model should be implemented in the software.

Self-Configurable Environment for the Intel Ixp2400 Network Processor

Network processors (NPs) are programmable multi-processor devices that offer both the flexibility and speed required for the network packet processing applications. Current NP systems do not simultaneously deal well with fluctuating workloads. Because of the traffic fluctuations inherent in packet networks, the workload on each pipeline stage in NP may vary significantly over time, thus affecting performance. One solution would be to change the code running at these stages so as to adapt to the fluctuations. Hence, the allocation of processors to pipeline stages needs to be adapted over time. Run-time adaptation is a potential solution to this problem. With run-time adaptation, the mapping of services to system resources can be dynamically adjusted based on the workload. Dynamically adapting processor allocations reduces the overall resource provisioning requirement for the system. This results in achieving robustness to traffic fluctuations. In this paper, we focus on reconfiguring the system based on the traffic fluctuation. To make decision about the deployment of code, the traffic is monitored and its statistic is maintained. Moreover, active network concept is used for reconfiguring the system, wherein the binary code is transferred to the NP through the SOAP protocol.

Adaptive Processor Allocation for Moldable Jobs in Computational Grid

In a computational grid environment, a common practice is try to allocate an entire parallel job onto a single participating site. Sometimes a parallel job, upon its submission, cannot fit in any single site due to the occupation of some resources by running jobs. How the job scheduler handles such situations is an important issue which has the potential to further improve the utilization of grid resources as well as the performance of parallel jobs. This article develops adaptive processor allocation policies based on the moldable property of parallel jobs to deal with such situations in a heterogeneous computational grid environment. The proposed policies are evaluated through a series of simulations using real workload traces. The results indicate that the proposed adaptive processor allocation policies can further improve the system performance of a heterogeneous computational grid significantly.

On submesh allocation for 2D mesh multicomputers using the free-list approach: Global placement schemes

Two global placement schemes for contiguous processor allocation in two-dimensional mesh-connected multicomputers are proposed in this paper. The first scheme gives preference to allocating a free peripheral submesh that has the largest number of mesh-boundary processors. This peripheral placement has for goal producing large leftover free submeshes, which can improve system performance. Another characteristic of this scheme is that it reduces the search space by halting the search process when a large-enough multicomputer corner submesh is found. The second proposed scheme considers allocation in the corners of all large-enough free submeshes and allocates a submesh that has the maximum number of allocated neighbors and multicomputer peripheral nodes. Using extensive simulations, we evaluated the proposed schemes and compared them with previous promising schemes. The simulation results show that the peripheral placement scheme produces the best average turnaround times, and its measured allocation and de-allocation times are smaller than those of the previous schemes. The second proposed scheme ranks overall second in terms of turnaround times, however it is last in terms of efficiency.

Adaptive hierarchical scheduling policy for enterprise grid computing systems

In an enterprise grid computing environments, users have access to multiple resources that may be distributed geographically. Thus, resource allocation and scheduling is a fundamental issue in achieving high performance on enterprise grid computing. Most of current job scheduling systems for enterprise grid computing provide batch queuing support and focused solely on the allocation of processors to jobs. However, since I/O is also a critical resource for many jobs, the allocation of processor and I/O resources must be coordinated to allow the system to operate most effectively. To this end, we present a hierarchical scheduling policy paying special attention to I/O and service-demands of parallel jobs in homogeneous and heterogeneous systems with background workload. The performance of the proposed scheduling policy is studied under various system and workload parameters through simulation. We also compare performance of the proposed policy with a static space–time sharing policy. The results show that the proposed policy performs substantially better than the static space–time sharing policy.

Design and performance evaluation of combined first-fit task allocation and migration strategies in mesh multiprocessor systems

In this paper, we consider the problem of processor allocation on mesh-based multiprocessor systems. We employ the idea of using migration to minimize fragmentation and the overall processing time of the tasks. In our schemes, we consider the use of task migration whenever required to improve the problem of fragmentation. To this end, we propose three efficient schemes to improve the performance of first-fit allocation strategies commonly used in practice. The first scheme, called the first-fit mesh-bifurcation (FFMB) scheme, attempts to start the search for a free submesh from either the bottom-left corner or the top-left corner of the mesh so as to reduce the amount of fragmentation in the mesh. The next two schemes, called the online dynamic compaction-single corner (ODC-SC) and online dynamic compaction-four corners (ODC-FC) schemes, use task migration to improve the performance of existing submesh allocation strategies. We perform rigorous simulation experiments based on practical workloads as reported in the literature to quantify all our proposed schemes and compare them against standard schemes existing in the literature. Based on the results, we make clear recommendations on the choice of the strategies.

Guest Editor Introduction: Special Issue on Multiprocessor-based Embedded Systems

The hardware and software architectures of embedded systems have undergone a significant evolution with the increase in their functional complexity and performance expectations. Embedded systems are no longer necessarily characterised by a single fixed application. The need to execute several different, although related, applications, combined with time-to-market pressures have led to architectures with multiple processors on a system-on-a-chip (SoC). This brings back into relevance traditional multiprocessor environments: processor allocation and task scheduling become important topics; integration of software and the building of abstraction layers to make it immune to changing of underlying hardware platforms becomes essential; and network and communication architectures need careful analysis. However, the domain-specific nature of embedded systems continues to lead to new challenges and optimisation opportunities. Making the hardware architecture flexible leads to several new interesting problems which can partially reuse existing multiprocessor related solutions, but also need fundamental innovations to extract efficiency. In this edition we present invited papers from several leading research groups on the topic of multiprocessor-based embedded systems. In the paper “A fast and accurate technique for mapping parallel applications on stream-oriented MPSoC platforms with communication-awareness”, Ruggeiro et al. present a framework for task allocation and scheduling in a multi-processor on chip platform. The combination of integer programming with constraint programming is demonstrated to result in optimal solutions reasonably fast. This approach helps improve performance for multiprocessor based systems that are not susceptible to

Performance of parallel computations with dynamic processor allocation

In parallel adaptive mesh refinement (AMR) computations the problem size can vary significantly during a simulation. The goal here is to explore the performance implications of dynamically varying the number of processors proportional to the problem size during simulation. An emulator has been developed to assess the effects of this approach on parallel communication, parallel runtime and resource consumption. The computation and communication models used in the emulator are described in detail. Results using the emulator with different AMR strategies are described for a test case. Results show for the test case, varying the number of processors, on average, reduces the total parallel communications overhead from 16 to 19% and improves parallel runtime time from 4 to 8%. These results also show that on average resource utilization improves more than 37%.

Communication-Aware Processor Allocation for Supercomputers: Finding Point Sets of Small Average Distance

We give processor-allocation algorithms for grid architectures, where the objective is to select processors from a set of available processors to minimize the average number of communication hops. The associated clustering problem is as follows: Given n points in ℜ d, find a size-k subset with minimum average pairwise L 1 distance. We present a natural approximation algorithm and show that it is a $\frac{7}{4}$-approximation for two-dimensional grids; in d dimensions, the approximation guarantee is $2-\frac{1}{2d}$, which is tight. We also give a polynomial-time approximation scheme (PTAS) for constant dimension d, and we report on experimental results.

Availability-based noncontiguous processor allocation policies for 2D mesh-connected multicomputers

Various contiguous and noncontiguous processor allocation policies have been proposed for mesh-connected multicomputers. Contiguous allocation suffers from high external processor fragmentation because it requires that the processors allocated to a parallel job be contiguous and have the same topology as the multicomputer. The goal of lifting the contiguity condition in noncontiguous allocation is reducing processor fragmentation. However, this can increase the communication overhead because the distances traversed by messages can be longer, and messages from different jobs can interfere with each other by competing for communication resources. The extra communication overhead depends on how the allocation request is partitioned and mapped to free processors. In this paper, we investigate a new class of noncontiguous allocation schemes for two-dimensional mesh-connected multicomputers. These schemes are different from previous ones in that request partitioning is based on the submeshes available for allocation. The available submeshes selected for allocation to a job are such that a high degree of contiguity among their processors is achieved. The proposed policies are compared to previous noncontiguous policies using detailed simulations, where several common communication patterns are considered. The results show that the proposed policies can reduce the communication overhead and improve performance substantially.

Solving a real-time allocation problem with constraint programming

In this paper, we present an original approach (CPRTA for “Constraint Programming for solving Real-Time Allocation”) based on constraint programming to solve a static allocation problem of hard real-time tasks. This problem consists in assigning periodic tasks to distributed processors in the context of fixed priority preemptive scheduling. CPRTA is built on dynamic constraint programming together with a learning method to find a feasible processor allocation under constraints. Two efficient new approaches are proposed and validated with experimental results. Moreover, CPRTA exhibits very interesting properties. It is complete (if a problem has no solution, the algorithm is able to prove it); it is non-parametric (it does not require specific tuning) thus allowing a large diversity of models to be easily considered. Finally, thanks to its capacity to explain failures, it offers attractive perspectives for guiding the architectural design process.