Process , Voltage And Temperature Research Articles

INDIDO: A novel low-power approach for domino logic circuits

Power dissipation in Nanoelectronic circuits at advanced technology nodes is dominated by leakage power dissipation. This is due to an increase in short channel effects in the scaled transistors.The VLSI industry is seeking alternative options to enhance the performance of portable electronic systems by ensuring higher speed and reduced power dissipation. In the ultra-deep submicron (DSM) regime, a new device called the fin-shaped field effect transistor (FinFET) was developed to replace CMOS technology. FinFET, a multi-gate device, significantly reduces power dissipation compared to planer MOS (Metal Oxide Semiconductor ) transistor, but it doesn’t entirely resolve the issue. To further reduce power dissipation in the ultra DSM regime, low power approaches are required. Domino logic, a widely-used dynamic logic, is commonly utilized in high-speed VLSI architectures. In this research work, a novel INput Dependent Inverter DOmino (INDIDO) logic approach for low-power domino logic circuits using FinFET devices is proposed. A comparative analysis between the proposed INDIDO method and the existing approaches is performed for domino logic circuits for various performance metrics at the 16 nm technology node. In this research, various circuits like domino buffer, domino OR, domino AND, domino XOR and domino half adder are designed using the proposed INDIDO approach.The proposed INDIDO FinFET buffer circuit offers significant improvement in energy efficiency and FOM (Figure of Merit) by 53.18% and 82% respectively as compared to conventional FinFET footed domino buffer circuit. Beside this, proposed circuits like INDIDO OR, INDIDO AND, INDIDO XOR and INDIDO Half adder circuit follow the same trend as INDIDO buffer circuit and show better performance parametres in comparison to the existing low power domino approaches as well. In addition to this, the proposed INDIDO buffer circuits are also analyzed for PVT(process voltage and temperature) variability.This whole analysis makes us to conclude that proposed INDIDO approach reduces power dissipation and delay penalty, have high noise tolerance capacity, more immunity against PVT variations and high energy efficiency in comparison to the already existing techniques.

Design and Comparison of Constant Transconductance Architectures

Constant transconductance (Gm) biasing circuits, as the name suggests, generate a bias current that ensures that the Gm of a MOS transistor remains constant. The Gm of a MOS transistor is a very important parameter as various other parameters of a circuit such as the gain, UGB (Unity Gain Bandwidth, poles, and zeros are strongly dependent upon it. Every analog circuit in a chip is subjected to varying PVT (Process, Voltage, and Temperature) conditions. This leads to a varying Gm of the devices, and hence the parameters such as the gain and UGB also tend to vary. Hence, constant Gm biasing is crucial in systems, where the parameters are expected to be constant regardless of the external factors. The majority of constant Gm biasing circuits make use of an external off-chip resistor. While this is a reasonable solution, it adds to the cost, area, and complexity of the solution. Hence, it is vital to model and design all the required functionalities within the chip, eliminating the requirement for any external components. In this paper, different architectures of constant Gm biasing circuits are designed and simulated in Cadence Virtuoso software. The proposed architecture has an error of 6.42% in the variation of transconductance, which is a significant improvement concerning the other architectures simulated. Additionally, the proposed architecture does not require any off-chip components while the other architectures require an off-chip resistor. Hence, the proposed solution has reduced cost and complexity.

Design and analysis of 7-stage MOS current mode logic power gated MOSFETs in current starved voltage-controlled oscillator for the phase locked loop application

This paper presents a new process, voltage and temperature (PVT) tolerant 7-stage ring type current starved voltage-controlled oscillator (CS-VCO). In this, a 7-stage ring VCO is proposed using power gated technique for phase locked loop (PLL) application. PLL plays a major role in clock and data recovery, Global Positioning System (GPS) system and satellite communications. For the high-speed application of PLL it is designed using 7-stage inverter delay cell with MOS current mode logic (MCML) technique. The circuit undergoes process, voltage and temperature variations with different parameters such as average power, oscillation frequency, phase noise, tuning range and output noise. The Monte-Carlo analysis justifies the proposed design provides better results. The circuit is simulated under 45 nm CMOS technology using cadence virtuoso. The average power consumption of the proposed circuit is 29.368 µW with the oscillation frequency of 3.06 GHz. The output noise and the phase noise of the proposed VCO are -161.55 dB and -125.92 dBc/Hz respectively. It achieves the frequency tuning range (FTR) of 95.09%. The obtained simulation results are highly robust with PVT making the circuit suitable for PLL application.

Impact of Variability on Novel Transistor Configurations in Adder Circuits at 7nm FinFET Technology

This research work focuses on implementation of the FinFET-based complementary metal-oxide-semiconductor (CMOS) Full Adder circuits for different transistor configurations using ASAP7 FinFET model. First, this work examines FinFET-based AND-OR-invert (AOI) gates using different topologies, and second, a FinFET-based CMOS Full Adder circuit at the 7[Formula: see text]nm technology node is analyzed with respect to its process, voltage and temperature (PVT) variability effect measured in terms of the normalized standard deviation of different performance metrics. The comparison is made between conventional (CFFA1) and proposed (FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8) FinFET-based CMOS full adder circuits. The aim is to determine the optimal design configuration of the FinFET full adder circuit with the minimum impact of PVT variability. On examining the power delay product (PDP) variability, it is found that variations in FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8 are significantly lower than CFFA1 by 6.30%, 4.68%, 10.30%, 65.48%, 68.05%, 65.61% and 17.20%, respectively. Among all the proposed configurations, normalized standard deviation [Formula: see text] for the PDP metric is lowest in FFA6, followed by FFA7, FFA5, FFA8, FFA4, FFA2 and FFA3. The normalized standard deviation [Formula: see text] for power dissipation, however, is lowest in FFA8. In addition, a layout comparison analysis of conventional and proposed full adder circuits reveals that FFA7 has the least area, followed by FFA8, FFA6, FFA5, FFA3, FFA4, FFA2 and CFFA1. The area of FFA2, FFA3, FFA4, FFA5 and FFA6 has decreased by 3.29%, 3.51%, 3.50%, 5.14% and 5.52%, while FFA7 and FFA8 have experienced a decrease in area by 13.87% and 14.36%, respectively, as compared to conventional CFFA1. The proposed layout of FinFET-based CMOS Full Adders can be directly transferred into the foundry’s production line for manufacturing purposes. The overall investigation led us to conclude that FFA8 is the most efficient of all due to the lowest power variation, lower delay variation and lower PDP variation, moreover it has a reduced layout area among all the discussed designs. However, there is a tradeoff in terms of penalty in nominal power, propagation delay and PDP in the proposed topologies.

A Low-Cost Triple-Node-Upset Self-Recovery Latch Design

As the CMOS process continues to decrease in size, the latch becomes increasingly vulnerable to the triple-node-upset (TNU), leading to a decrease in circuit reliability in harsh radiation environments. In this paper, a low-cost TNU self-recovery latch (LCTR) is proposed, which is based on one PMOS and two NMOS (1P2N) inverters and C-elements (CEs) forming a multi-level feedback loop. Due to the error interception function of these fundamental elements, the proposed latch completely realizes TNU self-recovery capability. Then the simulated tests are used for comparing the overhead of the LCTR latch and the other two typical TNU self-recoverable latches. The results reveal that the LCTR latch decreases power consumption by 56.98%, delay by 30.08%, area by 21.25% and PDP by 70.77%, respectively. Moreover, the LCTR latch is moderately sensitive to the variation of process, voltage and temperature (PVT).

Low-Leakage Double-Body MOSFET: A Promising Circuit-Level Technique for Deep-Submicron Analog Integrated Circuit Design

Since the leakage currents are dramatically increasing while the MOS transistors scale down to deep-submicron processes, the [Formula: see text]–[Formula: see text] characteristic of the channel is varied unintentionally. As a result, the analog integrated circuit (IC) designs based on it (at above 100-nm technologies) will malfunction. In this paper, a novel low-leakage double-body MOSFET (LLDB-M), as a circuit-level scheme in answering to the need for the current-mode analog IC design in deep-submicron processes, is proposed. In this technique, the sub-threshold and gate-oxide tunneling leakage currents (as two major parts) are reduced via lowering the gate-source voltage and increasing the threshold voltage of the MOS transistor. An LLDB-M consists of two typical transistors — the first one is the main transistor and the latter implements the shift-voltage to reduce the gate-source voltage and floor of the channel leakage currents. The drain, gate, and body of the main transistor as well as the body and source of the second one, organize the terminals of an LLDB-M. The proposed LLDB-M transistors are replaced with large-leakage transistors in a translinear loop in the weak inversion region and then the commonly-used circuits such-as the current mirror, one-quadrant multiplier-divider (at both up-down and stack topologies), the true RMS-DC converter, and the log-domain low-pass-filter are designed. The effectiveness and performance of the proposed LLDB-M technique and circuits are evaluated using HSPICE software in 22-nm BSIM4 CMOS process and Cadence Virtuoso tool in 65-nm TSMC CMOS technology. Post-layout simulation results show that the proposed circuit-level method by considerably reducing leakage currents could ensure the effective function of the current-mode analog IC designs in deep-submicron technologies. Also, comprehensive simulations have been performed to prove the robustness and reliability of the proposed circuits against process, voltage and temperature (PVT) changes.

Design and analysis of PVT tolerant hybrid current starved ring VCO with bulk driven keeper technique at 45 nm CMOS technology for the PLL application

This article introduces a novel approach of hybrid current-starved ring voltage-controlled oscillator (VCO) to overcome the challenges present in the Phase-locked loop (PLL) in high-frequency applications. In this, two novel VCO designs are proposed. The first design is the current starved pull-up sleepy ring VCO which offers improved frequency of oscillation and reduced phase noise. The second design utilizes a hybrid current starved ring VCO with the bulk-driven keeper technique which yields better results by reducing the power consumption and mitigating leakage current. The proposed circuit is analysed with various process corners and performs parametric analysis and Monte-Carlo analysis to verify the robustness of the circuit using Cadence Virtuoso tool with 45 nm gpdk library. The average power of the proposed −2 circuit is 7.38 µW, and it achieves an oscillation frequency of 6.965 GHz at 1 V supply. It has low phase noise of −121.49dBc/Hz at 1 MHz, and the output noise of −166.42 dB. The obtained figure of merit (FOM) is −185.95dBc/Hz. The proposed design exhibits a frequency tuning range of 92.8 %. The results clearly demonstrate that the proposed design is extremely tolerant to PVT (process, voltage, and temperature) variations making it well suitable for high-frequency PLL applications.

A Power-Gated 8-Transistor Physically Unclonable Function Accelerates Evaluation Speeds

The proposed 8-Transistor (8T) Physically Unclonable Function (PUF), in conjunction with the power gating technique, can significantly accelerate a single evaluation cycle more than 100,000 times faster than a 6-Transistor (6T) Static Random-Access Memory (SRAM) PUF. The 8T PUF is built to swiftly eliminate data remanence and maximise physical mismatch. Moreover, a two-phase power gating module is devised to provide controllable power on/off cycles for the chosen PUF clusters in order to facilitate fast statistical measurements and curb the in-rush current. The architecture and hardware implementation of the power-gated PUF are developed to accommodate fast multiple evaluations of PUF Responses. The fast speed enables a new data processing method, which coordinates Dark-bit masking and Multiple Temporal Majority Voting (TMV) in different Process, Voltage and Temperature (PVT) corners or during field usage, hence greatly reducing the Bit Error Rate (BER) and the hardware penalty for error correction. The designs are based on the UMC 65 nm technology and aim to tape out an Application-Specific Integrated Circuit (ASIC) chip. Post-layout Monte Carlo (MC) simulations are performed with Cadence, and the extracted PUF Responses are processed with Matlab to evaluate the 8T PUF performance and statistical metrics for subsequent inclusion in PUF Responses, which comprise the novelty of this approach.

A highly robust RF 65 nm CMOS power amplifier design using Quasi-Newton control algorithm for wireless system

This article reports a novel robust approach towards CMOS power amplifier (PA) using Quasi-newton (QN) control algorithm in 65 nm CMOS process which provides best performance parameters over redundant wide bandwidth ranging from 2.4 to 16.4 GHz frequency band. Each stage are designed and optimized using QN algorithm to get desired goals such as high linearity, small group delay variations and high PAE across the entire frequency band of interest. Moreover, pole-zeros compensation technique is adopted and derived to get better stability of the proposed PA. The simulation and measurement results of PA achieved a small signal power gain of 10.5–16.8 dB with input return loss of better than 10 dB over the frequency band of 2.4 GHz to 16.4 GHz. A small group delay variation of ±58 ps over full frequency band of operation is achieved by optimizing the design parametric analysis. It is also observed that within the frequency of 6.5 to 14.6 GHz, an excellent small group delay variation of only ±11 ps is achieved and this is due to stage-2 tuning compensation technique. It also demonstrates the achieved input power in 1 dB compression points are −3.1 to 4.3 dBm, leading to maximum power added efficiency of 36.3%, respectively. The proposed PA consumes a lower DC power of 20.5 mW under supply voltage of 1.5. In addition, Process, voltage and temperature (PVT) analysis is executed at different conditions in order to achieve a robustness of the proposed PA over the entire band of operation.

Asynchronous Sampling-Based Hybrid Equalizer

An equalizer architecture based on asynchronous sampling is described. The circuit implementation is a hybrid feed-forward equalizer (FFE) using three digital postcursor taps realized via level-crossing samplers (LCSs) and inverter-based delays. Utilizing a current mode logic (CML)-based summer stage, an analog main tap and digital postcursor taps are combined into an inductively tuned resistor load. With a 0.67-mV-rms simulated output-referred noise, the FFE has better noise performance than a conventional continuous-time linear equalizer (CTLE) and a slicer/latch-based decision feedback equalizer (DFE) circuit. Moreover, it exhibits very good linearity and group delay performance suitable for an equalizer. Using inverter-based delays enables area efficiency as well as the capability to tune the delay across process voltage and temperature (PVT) variations. Since the FFE is an event-driven combinational logic based on the incoming data, it does not require synchronous sampling coming from a high-speed clock and data recovery (CDR), and it is advantageous for high-speed and multirate operation as its power consumption scales with the data rate. Fabricated in 40-nm CMOS technology, the hybrid FFE achieves energy per bit of 2.7 pJ/bit with a 20-dB Nyquist insertion loss link at the 28.57-Gb/s nonreturn to zero (NRZ) data rate.

A False Trigger-Strengthened and Area-Saving Power-Rail Clamp Circuit with High ESD Performance.

A power clamp circuit, which has good immunity to false trigger under fast power-on conditions with a 20 ns rising edge, is proposed in this paper. The proposed circuit has a separate detection component and an on-time control component which enable it to distinguish between electrostatic discharge (ESD) events and fast power-on events. As opposed to other on-time control techniques, instead of large resistors or capacitors, which can cause a large occupation of the layout area, we use a capacitive voltage-biased p-channel MOSFET in the on-time control part of the proposed circuit. The capacitive voltage-biased p-channel MOSFET is in the saturation region after the ESD event is detected, which can serve as a large equivalent resistance (~106 Ω) in the structure. The proposed power clamp circuit offers several advantages compared to the traditional circuit, such as having at least 70% area savings in the trigger circuit area (30% area savings in the whole circuit area), supporting a power supply ramp time as fast as 20 ns, dissipating the ESD energy more cleanly with little residual charge, and recovering faster from false triggers. The rail clamp circuit also offers robust performance in an industry-standard PVT (process, voltage, and temperature) space and has been verified by the simulation results. Showing good performance of human body model (HBM) endurance and high immunity to false trigger, the proposed power clamp circuit has great potential for application in ESD protection.

A 39-GHz CMOS Bidirectional Doherty Phased- Array Beamformer Using Shared-LUT DPD With Inter-Element Mismatch Compensation Technique for 5G Base Station

This article demonstrates a 39-GHz CMOS phased-array beamformer aiming for power-efficient and area-efficient fifth-generation (5G) dual-polarized multiple-in–multiple-out (DP-MIMO) applications. To address the digital pre-distortion (DPD) implementation issue in the massive beamformer elements with Doherty technique integrated, an inter-element mismatch compensation technique is introduced for improving the shared-lookup table (LUT) DPD performance over the process, voltage and temperature (PVT) variations. A bidirectional Doherty power amplifier (PA)-LNA is proposed to enhance the power back-off (PBO) efficiency regarding the high peak-to-average power ratio (PAPR) 5G signals, meanwhile cost down the system by the unbalanced neutralized bidirectional operation. The proposed phased-array beamformer chip is fabricated in 65-nm CMOS technology and packaged in a wafer-level chip-scale package (WLCSP). Each element occupies only a 0.82-mm2 chip area, including the on-chip low-dropout regulator (LDO). The measured stand-alone Doherty PA-LNA achieves 18.9-dBm saturated output power with 17.8% power-added efficiency (PAE) at 6-dB PBO in PA mode and obtains a 4.8-dB noise figure (NF) at 40 GHz in LNA mode. By utilizing the proposed mismatch compensation, the measured 64-quadrature amplitude modulation (QAM) orthogonal frequency-division multiple access (OFDMA)-mode error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR) with the shared-LUT DPD are improved from −22.4 to −25.0 dB and from −28.7 to −32.1 dBc, respectively. The 64-element module achieves a 55.2-dBm saturated effective isotropic radiated power (EIRP) and supports 21-Gb/s single-carrier (SC) mode data streaming. The measured 64-element transmitter (TX) EVM is −25.2 dB at 43.2 dBm with 3.5-GSymbol/s baud rate in 64 QAM, and the corresponding 64-to-4 elements TX-to-receiver (RX) EVM is −22.5 dB. The consumed power for each element is 402 mW at saturation output point in TX mode and 87 mW in RX mode.

Design of fully differential fast SCL Schmitt-trigger delay element with tunable delay and hysteresis in design and run-time

Tuning the delay of the circuit during the circuit performance can give a chance to a circuit to reduce Process, Voltage and Temperature (PVT) effects on delay and frequency by resetting its delay in feedback. This paper presented a full differential Schmitt-trigger (ST) with tunable delay and hysteresis. The delay-hysteresis setting is done in the design phase by tuning the biasing current, sizing, bias voltage and also during the execute phase (run time) by a digital bit and restructuring the circuit and delay route. The presented ST can have high and low delays with different frequencies using a digital bit in the circuit. This can help the band selection for multi-band applications. A Flip Voltage Follower (FVF) circuit is used for the current tail to increase the current and increase the frequency bands. In this Schmitt-trigger delay changes associated with restructuring result in a 40 % power reduction. A circuit analysis for the equivalent circuit of the presented circuit has also been done and the factors affecting the frequency and delay change have been analyzed and investigated in the simulation. Monte Carlo and PVT analysis have also been performed for circuit accuracy. Power changing with an incremental delay in CMOS is improved and almost monotonous by designing Source-Coupled-Logic (SCL) Schmitt-trigger.

A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process

This paper presents a 2 × VDD mixed-voltage digital output buffer where its slew rate (SR) is automatically adjusted based on PVT (process, voltage, and temperature) detection. The developed buffer is the first to be fabricated using TSMC 16-nm CMOS Logic FinFET Compact (Shrink) LL ELK Cu 1P13 M process. Since slew rate is one of the major required parameters in many interfacing protocols, it is really hard to meet if the mixed-voltage output buffer is needed in FinFET processes. The major reason is the low VDD in these advanced processes. However, our buffer's SR is improved by implementing low threshold voltage (Vth) type of device for always-on driving transistors in the Output Stage, thereby increasing the output current. Moreover, since FinFET devices were used in the buffer, the stability of the gate drives of the said driving transistors must be ensured so that noise interference will be avoided. Lastly, the buffer's Timing Shifters used non-overlapping signaling control directly implemented at the transistor level to eliminate the errors caused by delay variations. Based on silicon measurement results, at a load capacitance of 20 pF, the said circuit can be operated at a maximum data rate of 250 MHz for both supply voltages of 0.8 and 1.6 V (namely external VDD or VDDIO), respectively. When the SR auto-adjustment is activated, the SR improvement is at least 49.2% and 37.5% for 0.8 and 1.6 V, respectively.

A Real-Time Electronically Tunable All-MOS Universal Biquadratic Voltage-Mode Filter

— In this paper, an electronically tunable universal biquadratic voltage-mode filter that is based only on MOS transistors is proposed. Configuration of the proposed filter is simple and there is no need to use component matching. Since the proposed filter contains only MOS transistors, it is very suitable for implementation in system-on-chip (SoC) applications. The cutoff frequency of the lowpass (LP) and highpass (HP) filters as well as the center frequency and the bandwidth of the bandpass (BP) and bandstop (BS) filters can be controlled either in a continuous range or in a discrete manner by means of a digital control word. Besides, the filter type can be changed during the real time by an appropriate code. Operation of all the filtering functions are verified by simulation using the Berkeley predictive-technology models (BPTM) of the 130 nm complementary metal-oxide semiconductor (CMOS) technology with power-supply voltage, VDD, of 1.2 V. The proposed filter is analyzed quantitatively, and the effects of the total-harmonic distortion (THD), noise, process, voltage and temperature (PVT) variations are also investigated. The average power consumption of the LP, HP, BP, BS, and allpass (AP) filters are found to be 30, 118, 74, 118, and 30 (all in µW). The price paid for all these advantages is more sensitivity to process variations for the lowpass filter.

A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch Design

In this article, a high-performance and low-cost single-event multiple-node-upsets resilient (HLMR) latch is proposed in 55-nm CMOS technology. By using eight normal two-input Muller-C-elements (MCEs) and eight clock-gating (CG)-based two-input MCEs, a feedback loop storage module with 16 storage nodes is constructed, which makes the latch completely triple-node-upsets (TNUs) resilient. Meanwhile, through the special layout technique which guarantees the worst quadruple-node pairs as physically apart as possible, the proposed latch is completely quadruple-node-upsets (QNUs) tolerant and almost completely QNU resilient. Simulation results have validated the robustness and low cost of the proposed latch due to the use of high-speed transmission gates (TGs), CG technology, and fewer transistors. Overhead comparisons indicate that our design saves 383.53% area-power-delay product (APDP) on average and has a lower sensitivity on process, voltage and temperature (PVT) compared with other considered up-to-date multiple-node-upsets (MNUs) tolerant latches, thus providing high reliability for safety and low-cost critical applications, especially in harsh radiative environments.

A Differential-to-Single-Ended Converter Based on Enhanced Body-Driven Current Mirrors Targeting Ultra-Low-Voltage OTAs

In this work, an ultra-low-voltage (ULV) technique to improve body-driven current mirrors is proposed. The proposed technique is employed to improve the performance of conventional differential-to-single-ended (D2S) converters which at these low voltages suffer from a low common-mode rejection ratio (CMRR). In addition, the technique aims to improve the performance of the conventional D2S also under a large signal swing and with respect to the process, voltage and temperature (PVT) variations, resulting in a very low distortion, high current mirror accuracy and robust performance. An enhanced body-driven current mirror was designed in a 130nm CMOS technology from STMicroelectronics and an exhaustive campaign of simulations was conducted to confirm the effectiveness of the strategy and the robustness of the results. The enhanced D2S was also employed to design a ULV operational transconductance amplifier (OTA) and a comparison with an OTA based on a conventional D2S was provided. The simulation results have shown that the proposed enhanced D2S allows achieving the ULV OTAs with a CMRR and a PSRR which are 18 and 9 dB higher than the ones obtained with the conventional D2S topology, respectively. Moreover, the linearity performance is also improved as shown by the THD, whose value is decreased of about 5 dB.

Design of a Power Regulated Circuit with Multiple LDOs for SoC Applications

In this paper, a power regulated circuit (PRC) is proposed for system-on-a-chip (SoC) applications. The proposed PRC is composed of a limiter, a bandgap reference (BGR), three low-dropout regulators (LDOs), and a bias generator. A high output voltage of an active rectifier is given to the limiter, which limits it to a desired supply voltage for circuits in PRC. The curvature-compensated BGR robust to process, voltage and temperature (PVT) variations are designed to provide a stable reference voltage for three LDOs. The three LDOs are implemented to generate regulated output dc voltages. The proposed PRC is designed and fabricated in 130 nm bipolar-CMOS-DMOS (BCD) technology with die area of 1.9 mm × 0.860 mm, including pads. The measurement results show that the limiter limits the input voltage of (6 V to 20 V) to 5.3 V. The BGR produces a stable reference voltage of 1.24 V with a power supply rejection ratio (PSRR) of −58.6 dB and −51.9 dB at 10 Hz and 1 kHz, respectively. The LDO_5V, LDO_3V, and LDO_1.5V generate regulated output dc voltages of 5 V, 3 V, and 1.5 V, respectively, with dc load regulations of 0.43 mV/mA, 0.70 mV/mA, and 0.28 mV/mA while delivering load currents of 300 mA, 100 mA, and 100 mA, respectively.

Low Power Squaring Circuit Using Single Voltage Differencing Buffered Amplifier

In this paper, a squaring circuit is proposed using a voltage differencing buffered amplifier (VDBA). The squaring circuit consists of a VDBA, two NMOS transistors and one resistor. The proposed structure facilitates easy cascading without any requirement of additional buffer. The behavior of the proposed structure is analyzed in the presence of nonidealities of VDBA and the corresponding mathematical formulations are also presented. The workability of the proposed circuit is verified through Cadence Virtuoso Analog Design Environment tool using 0.18[Formula: see text][Formula: see text]m generic process design kit parameters. Both pre- and post-layout simulation results have been included to confirm the functionality of the proposed circuit. The 3-dB frequency of the proposed circuit using schematic and post-layout-driven simulations is observed to be 3.77 and 3.72[Formula: see text]MHz, respectively. The power consumption of the proposed squaring circuit is found to be 110[Formula: see text][Formula: see text]W. The process, voltage and temperature (PVT) analysis has also been carried out to check the robustness of the proposed circuit. Total harmonic distortion for the entire input range is found to be less than 3%.

A Novel Energy Efficient and Process Immune Schmitt Trigger Circuit Design Using FinFET Technology

Continuous scaling of MOS (Metal oxide semiconductor) devices gives rise to drastic increase in leakage power dissipation, which overall increases the total power dissipation. This happens due to increase in short channel effects. FinFET device has the capability to reduce short channel effects, hence reduces power dissipation as well. In this paper short-gate FinFET (fin type field effect transistor) based Schmitt trigger using LCNT (Leakage Control NMOS transistor) technique is proposed using ASAP7 PDK (A 7nm FinFET Predictive process design kit) at 7nm technology node and comparative analysis is provided with the one without LCNT technique. The simulated results shows that FinFET based Schmitt trigger using LCNT technique reduces average power dissipation and power delay product (PDP) by 36.97% and 35.6%, respectively compared to one without FinFET LCNT technique. The reliability analysis using Monte Carlo approach at ±10% process, voltage and temperature (PVT) variation under 3σ Gaussian distribution shows that LCNT FinFET Schmitt trigger provides better performance compared to FinFET Schmitt trigger at 7nm technology node.