Process , Voltage And Temperature Research Articles

A Cascaded Noise-Shaping SAR Architecture for Robust Order Extension

The emerging noise-shaping (NS) successive approximation (SAR) architecture is highly efficient and compact; however, the order and signal-to-noise ratio (SNR) of sub-MHz NS SAR ADCs are still lower than conventional sigma-delta ADCs. This work proposes a cascaded NS (CaNS) SAR architecture that increases system order and enables more effective NS for higher SNR. The proposed architecture enhances the robustness of high-order NS performance at the system level and is inherently process, voltage and temperature (PVT) stable. A two-phase settling technique improves the efficiency of residue amplification without sacrificing robustness. A prototype CaNS SAR ADC, fabricated in 28-nm CMOS, occupies 0.02 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 120 μW. The measured Signal to Noise and Distortion Ratio (SNDR) over 100-kHz bandwidth is 88 dB, resulting in a Schreier Figure of Merit (FoM) of 177 dB.

Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths

This brief presents the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of-concept benchmark circuit is designed and fabricated in 65 nm technology. Measurements on 10 test chips, while considering supply voltages spanning 0.6V to 1.2V and temperature variations ranging from −40 °C to 125 °C confirm the effectiveness of this approach to compensate for severe process, voltage and temperature (PVT) variations.

A fast locking and low jitter hybrid ADPLL architecture with bang bang PFD and PVT calibrated flash TDC

In the present work, an all digital phase locked loop architecture (ADPLL) employing a bang-bang phase frequency detector (BB-PFD) and the 3-bit flash based time to digital converter (TDC) is designed to enhance the jitter and locking time performance. The proposed ADPLL utilizes a low power and high resolution 3-bit flash TDC with foreground calibration to suppress the issues of process, voltage and temperature (PVT) spreads and achieves low jitter and low power ADPLL. To obtain the fast locking, a proposed dynamic bang-bang PFD is used. The proposed ADPLL takes only 5 iterations to achieve the locking from unlocked state. Additionally, ADPLL employs a wide range and low phase noise voltage controlled oscillator (VCO) based on inverters to obtain a reduced jitter in ADPLL. The proposed ADPLL is designed in 180-nm SCL digital CMOS technology at 1.8 V supply. It consumes a total power of 5.94 mW at 1.8 V. From the post layout simulations, the achieved FoM and periodic jitter is −227.6 dB and 1.71 ps respectively at an output frequency of 1.6 GHz. The achieved phase noise of proposed ADPLL is −131.2 dBc/Hz at offset of 100 MHz.

A 1-nS 1-V Sub-1-µW Linear CMOS OTA with Rail-to-Rail Input for Hz-Band Sensory Interfaces.

The paper presents an operational transconductance amplifier (OTA) with low transconductance (0.62–6.28 nS) and low power consumption (28–270 nW) for the low-frequency analog front-ends in biomedical sensor interfaces. The proposed OTA implements an innovative, highly linear voltage-to-current converter based on the channel-length-modulation effect, which can be rail-to-rail driven. At 1-V supply and 1-Vpp asymmetrical input driving, the linearity error in the current-voltage characteristics is 1.5%, while the total harmonic distortion (THD) of the output current is 0.8%. For a symmetrical 2-Vpp input drive, the linearity error is 0.3%, whereas THD reaches 0.2%. The linearity is robust for the mismatch and the process-voltage-and-temperature (PVT) variations. The temperature drift of transconductance is 10 pS/°C. The prototype circuit was fabricated in 180-nanometer CMOS technology.

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space

The rise of data-intensive applications has resulted in an increasing demand for high-density and low-power on-chip embedded memories. Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible alternative to conventional static random access memory (SRAM) which offers higher density, lower leakage power, and two-ported operation. However, in order to maintain the stored data, GC-eDRAM requires periodic refresh cycles, which are determined according to the worst-case data retention time (DRT) across process, voltage and temperature (PVT) variations. Even though several DRT characterization methodologies have been reported in literature, they often require unfeasible run-times for accurate DRT evaluation, or they result in highly pessimistic design margins due to their inaccuracy. In this work, we propose an current-based DRT (IDRT) characterization methodology that enables accurate DRT evaluation across process variations without the need for a large number of costly electronic design automation (EDA) software licenses. The presented approach is compared with other DRT characterization methodologies for both accuracy and run-time across several gain-cell structures at different process technologies, providing less than a 4% DRT error and over $100\times $ shorter run-time compared to a conventional DRT evaluation methodology.

A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response

A variation-adaptive computational digital low dropout (CDLDO) regulator featuring an event-driven computational controller (CC) is presented, which computes the required number of power gates (PGs) unlike the traditional IIR filter-based control techniques to regulate the output voltage for any load/reference transient. The CC ensures ~ns transient response with a deterministic two-event duration settling time, independent of the dynamic range of the load or output capacitor value. Measurement results of a 10-bit PG design demonstrate a droop of 100 mV for 500 mA (2 A/ns $di/dt$ ) with settling times < 20 ns. The CDLDO design is presented with the key equations and timing diagrams to show the operating principle of the concept. Methods to accommodate resiliency to process, voltage and temperature (PVT) and wide dynamic voltage frequency scaling (DVFS) conditions are also discussed in detail.

A Positive Feedback-Based Op-Amp Gain Enhancement Technique for High-Precision Applications

A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to the previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65[Formula: see text]nm CMOS technology. It results in 81[Formula: see text]dB voltage gain, which is 21[Formula: see text]dB higher than the existing gain-boosting technique. The proposed op-amp works with as low a power supply as 0.8[Formula: see text]V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1[Formula: see text]V supply. The circuit draws a total static current of 295[Formula: see text][Formula: see text]A and occupies 5000[Formula: see text][Formula: see text]m2 of silicon area.

Ultra-low-power wideband NMOS LC-VCO design for autonomous connected objects

In this paper, a fully integrated sub threshold LC voltage controlled oscillator (VCO) is presented. A design methodology is also proposed to find the optimal parameters lowering the power consumption. This methodology has been applied to design oscillators for different frequency bands. Furthermore, an adaptive body biasing technique has been used to improve the startup constrains and allows a high immunity to PVT (process, voltage and temperature) variations. A VCO operating in 5 GHz ISM (Industrial, Scientific and Medical) band has been realized with the proposed methodology in 0.13 μm CMOS. It consumes only 468 μW from 0.39 V supply voltage. This makes it possible to meet the required specifications of autonomous connected objects and IoT applications. The measured oscillation frequency can be tuned from 5.14 to 5.44 GHz. The obtained phase noise is approximately equal to − 112 dBc/Hz in post-layout simulation (PLS) and − 104.5 dBc/Hz in measure.

Architecture of resistive RAM with write driver

As technological advancements are increasing in the world at a faster rate, the need of miniaturization is also growing parallelly. The scaling of existing MOS technology in nanometre regime has caused some limitations such as drastically increase in leakage current, power consumption and some quantum mechanical effects. This paper provides an insight of an alternative technology which makes use of new circuit element called memristor which can be successfully scaled at a lower nanometre regime. This paper proposes a new READ and WRITE circuitry to facilitate an easier read and write operation. The paper illustrates a transmission gate based 2T1M RRAM bit cell which uses memristor as a memory element and subjects it to process, voltage and temperature (PVT) variations with the aim of reflecting the improvement in performance metrices read and write delay along with the read current variability. The SPICE simulation results reflect that the proposed memory cell has a better stability due to its less read current variability against process variation (such as varying oxide thickness) and is robust with minimal variation in read/write delay with respect to the variations in voltage and temperature. The cell depicts shorter read and write delay compared to NAND and NOR CMOS based flash memories and it has 98.72%,94.53% lesser write time when compared to ambipolar transistor-based memory cell and memristor based content addressable memory (MCAM) respectively. The proposed cell also has 72.5% lesser read time compared to MCAM.

A Low-Voltage Robust Class-C VCO With Dual Digital Feedback Loops

This brief presents a low-supply-voltage robust class-C voltage-controlled oscillator (VCO) with the dual digital feedback loops. One is the digital adaptive bias loop (DABL) which is proposed to ensure startup robustness and improve the phase noise performance of the VCO. And the other is the digital amplitude control loop (DACL), which is adopted to stabilize the oscillation amplitude over process, voltage and temperature (PVT) variations. Moreover, a cooperative algorithm is also proposed in order to make the dual digital loops work properly. Besides, the offset canceling comparators are adopted to guarantee the stability of the digital loops. The proposed VCO is implemented in SMIC 0.18 $\mu \text{m}$ CMOS process, achieving a phase noise of −123.3 dBc/Hz at 1 MHz offset from a 2.55 GHz carrier and a 2.2-2.7 GHz frequency tuning range. The figure-of-merit (FoM) is −190.4 dBc/Hz with the total power consumption less than 1.28 mW at the 0.8 V supply voltage.

A sub-harmonic injection locking clock multiplier with FLL PVT calibrator

Using the sub-harmonic injection locking technique, an enhanced differential Digitally Controlled Ring Oscillator (DCRO) with improved phase noise performance is proposed in this paper. All circuit blocks were implemented using digital design flow and designed using a hardware description language. A Frequency Locked Loop-based Process, Voltage and Temperature (PVT) calibrator was utilized to overcome PVT variations. The design was fabricated in 65 nm CMOS technology and its area is 0.017 mm2. The measured phase noise at 1 MHz offset and RMS jitter are −128 dB/Hz and 197fs, respectively. The design was tested in the presence of voltage and temperature variations. The maximum jitter difference percentage is 13.7% at 70 °C and 1.1 V and the phase noise value changes by a maximum of 0.7 dB over the whole range of voltages and temperatures. Furthermore, when the design was tested in the presence of switching noise, it provides up to 7 dB improvement in phase noise when compared to a single ended version of the DCRO.

Design and analysis of INDEP FinFET SRAM cell at 7‐nm technology

AbstractThe reduction in size of metal oxide semiconductor (MOS) devices results in increase in leakage power dissipation, which occurs due to the short‐channel effects in subthreshold region. Now a day's power dissipation is one of the crucial issues that the modern electronic industry is facing. Fin‐type field‐effect transistor (FinFET) can be proven as a best substitute to reduce leakage power dissipation in logic circuits. Degradation of performance with process variations is of major concern and needs to design FinFET circuits with minimum leakage power dissipation. In this paper, static random‐access memory (SRAM) cell is designed using low power shorted‐gate (SG) FinFETs at 7‐nm technology to minimize leakage power dissipation besides improving other performance parameters like static noise margins (SNMs) and power delay product (PDP) as well. The various parameters are analyzed using butterfly and N‐curve methods. The ASAP7 PDK is used to design SRAM cells using Cadence Virtuoso tool. The simulated results show that FinFET input‐dependent (INDEP) technique reduces the leakage power dissipation by 32.08% and 13.50%, respectively, in read and write conditions of FinFET SRAM cell. The Monte‐Carlo simulation results show the reduction in average power using INDEP approach at ±10% process, voltage and temperature (PVT) variations under 3σ Gaussian distribution of FinFET SRAM cell.

Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation

Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V. The method used to verify the robustness of the comparator circuit across 45 PVT is presented. The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 100°C. The simulation result show that the proposed comparator circuit achieved significant reduction of power consumption and delay during worst case condition compared to dynamic comparator proposed from previous researchers.

A Fully Static True-Single-Phase-Clocked Dual-Edge-Triggered Flip-Flop for Near-Threshold Voltage Operation in IoT Applications

A Dual-Edge-Triggered (DET) flip-flop (FF) that can reliably operate at low voltage is proposed in this paper. Unlike the conventional Single-Edge-Triggered (SET) flip-flops, DET-FFs can improve energy efficiency by latching input data at both clock edges. When combined with aggressive voltage scaling, significant efficiency improvement is expected. However, prior DET-FF designs were susceptible to Process, Voltage and Temperature (PVT) variations, limiting their operation at low voltage regimes. A fully static true-single-phase-clocked DET-FF is proposed to achieve reliable operation at voltages as low as a near-threshold regime. Instead of the two-phase or pulsed clocking scheme in conventional DET-FFs, a True-Single-Phase-Clocking (TSPC) scheme is adopted to overcome clock overlap issues and enable low-power operation. Fully static implementation also enables robust operation in a low voltage regime. The proposed DET-FF is designed in 28nm CMOS technology, and a comprehensive analysis including post-layout Monte Carlo simulation for wide PVT ranges is performed to validate the design approaches. Extensive analysis and comparison with prior-art DET-FFs confirmed that the proposed DET-FF can operate at the lowest voltage of 0.28 V for a temperature range of −40 °C to 120 °C while maintaining nearly-best energy efficiency and power-delay-product.

Design and PVT Analysis of Robust, High Swing Folded Cascode Operational Amplifier

The folded cascode operational amplifier (FCOA) designed in this paper is the single-pole operational amplifier (op amp). In this design, the conventional current mirror is replaced with wide swing current mirror to overcome the essential drawback of cascode configuration. In this paper, negative feedback is used to improve the small-signal gain and to ensure better stability than multistage amplifiers. This paper also aims at improving the output voltage swing, power dissipation and robustness of the op amp. The designed FCOA is proficient in achieving 67.44dB gain and 1.77V output swingat typical voltage for 180nm CMOS technology. The FCOA is highly stable with phase margin of 62.58º while dissipating 0.5mW power. This amplifier is further verified for variability analysis for Process, Voltage and Temperature (PVT) variations to check robustness. All together testing is done at 45 different PVT combinations and results are tabulated accordingly. At each corner temperature and voltage are varied for all together nine combinations to properly address the effect of PVT variations. The results shows that the op amp exhibits desired response at four corners (FF, TT, SS, and FS) of process, over -40º to 125º C temperature range. Also it is capable of operating at very low voltage up to 0.9V adequately showing reduction in power dissipation. Thus the designed op amp is low power, high swing and robust towards process, voltage and temperature variations.

OCTAN: An On-Chip Training Algorithm for Memristive Neuromorphic Circuits

In this paper, we propose a hardware friendly On-Chip Training Algorithm for the memristive Neuromorphic circuits (OCTAN). Although the proposed algorithm has a simple hardware like that of the random weight change (RWC) algorithm, it is much more efficient in terms of convergence speed and accuracy. In this algorithm, weights of the circuit are updated individually by a small value and the effect of individual weight update is assessed. If the weight change causes an increase in the error of the network, the weight update is reversed by applying the same change in the reverse direction twice. The usefulness of the proposed algorithm is verified by training some neuromorphic circuits for different applications. Compared to RWC and stochastic least-mean-squares (SLMS) training algorithms, our proposed algorithm needs, on average, $329\times $ fewer epochs to find the minimum error point. Moreover, the accuracy of the networks trained by OCTAN is, on average, about 46% higher than those of RWC and SLMS algorithms. Additionally, a hardware for OCTAN is presented. This hardware provides a speedup of $172\times $ ( $61\times $ ) compared to that of the RWC (SLMS) algorithm. Finally, the impact of PVT (process, voltage, and temperature) variations is studied on the proposed training hardware indicating an average training error increase of less than 3.27% in the presence of variations.

A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR ADC

This paper proposes a low power 10-bit 2b/cycle time and voltage based-successive approximation register (SAR) analog-to-digital converter (ADC). At low supply voltage, there will be a significant difference in comparator decision time for different input voltages. By taking advantage of the fact, this ADC converts the reference voltage to the corresponding comparator decision time, achieving 2b/cycle quantization to improve the conversion speed. In addition, by obtaining reference delays with duplicated circuits and using non-binary capacitor arrays, the ADC can tolerate process, voltage and temperature (PVT) variations and decision errors. To validate these concepts, a 10-bit 2MS/s SAR ADC is designed using 130nm CMOS process with 0.5V power supply voltage. Measured results show that the ADC can work normally from 0.5V to 1V supply voltage, with the sampling rate increasing from 2MS/s to 32MS/s. The ADC achieves an SNDR (signal-to-noise distortion ratio) of 56.7dB, corresponding to an ENOB (effective number of bits) of 9.13 bits and consumes $3.4\mu \text{W}$ , resulting in a figure of merit (FoM) of 3.03 fJ/c.-s at 0.5V supply voltage and 2MS/s sampling rate.

A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC With Dual Rising-Edge Fractional-Phase Detector

A 77-GHz frequency-modulated continuous-wave (FMCW) generator is presented for millimeter-wave (mm-wave) radar applications. The FMCW chirp is provided by a mixed-mode phase-locked loop (PLL). A dual rising-edge fractional-phase detector based on time-to-digital converter (TDC) is proposed to overcome the problem caused by the rising and falling time mismatch. A 2.3 ns detection range, 10 ps resolution Vernier TDC is employed in the detector to cover the two consecutive rising edges with less power consumption. A self-calibrated delay chain is employed in the Vernier TDC to overcome process, voltage and temperature (PVT) variations. Furthermore, sampling-edge selection technique is utilized to avoid the glitch during phase detection. A divider-less frequency error estimator is presented to save area and power. By employing a coarse-fine segmented digital-to-analog converter (DAC), the generator supports triangular and sawtooth-like FMCW chirp with reconfigurable period and bandwidth. An LC voltage- controlled oscillator (VCO) with split varactor is proposed to improve the linear tuning range. Implemented in 65 nm CMOS, the FMCW generator consumes 99 mW power and 0.7 mm $\times $ 0.8 mm chip area. The measurement results show that the phase noise from 78.7 GHz carrier is −87.4-dBc/Hz at 1 MHz offset. The measured root-mean-square (RMS) frequency error of a sawtooth-like FMCW chirp with 4 GHz bandwidth and 0.1 ms period is 205 kHz.

A RF PVT Compensated Negative Resistance Circuit for Q-factor Improvement of Passive Elements in CMOS

A RF process, voltage and temperature (PVT) compensated negative resistance (NR) circuit is proposed to improve the quality factor (Q-factor) of CMOS passive devices while ensuring stability over PVT variations. It is implemented in the form of a grounded NR circuit to support single-ended RF circuit applications. Various circuit techniques such as a diode-connected load, a proportional-to-absolutetemperature (PTAT) current source and an adaptive body-biasing based threshold voltage compensation have been adopted to obtain a stable negative resistance value. Simulation results show that the Qfactor of on-chip spiral inductors loaded by the proposed NR circuit is improved from 6 to 60 at 1 ㎓ under typical corner conditions (tt, 1.2V, 27 ℃). The simulated Q-factor variation in corner conditions is approximately 37, which is approximately 6.5 times more stable than conventional NR circuit without compensation.

A high-precision current-mode multifunction analog cell suitable for computational signal processing

In this paper, a high linear, low-voltage two-quadrant current squarer as multifunction analog cell, is presented. To implement the squarer circuit, translinear loops with matched NMOS transistors operating in weak inversion region are used. The proposed cell is used as a basic building block for current-mode computational analog functions such as rectifier (absolute-value), multi-input vector summation and exponential function generator. We perform post-layout plus Monte Carlo simulations of the presented functions with 0.18 μm (level-49 parameters) TSMC CMOS technology that prove their superiority over some other advanced works and robustness against PVT (process, voltage and temperature) variations.