Process-induced Damage Research Articles

Process damage assessment of a low energy inductively coupled plasma-based neutral source

In this article, we report process damage studies using a low energy inductively coupled plasma-based neutral stream source. Low energy neutrals are generated by the surface reflection neutralization method. Quasistatic capacitance-voltage measurement results of this work demonstrate that this low energy neutral source, which provides controllable fast neutrals for cleaning applications, induces much less damage than a pulsed inductively coupled plasma source. Most of the neutral process damage is caused by ultraviolet photons escaping from the plasma source zone. The process-induced damage by fast neutrals increases as the reflector bias is lowered. The fast neutral process damage also increases with the rf power. Unlike the neutral process-induced damage, the damage induced by pulsed plasmas is found to be a function of both the gas composition and rf pulsed frequencies.

Influence of Gate Oxide Quality on Plasma Process-Induced Charging Damage in Ultra Thin Gate Oxide

The correlation between the gate oxide quality and the plasma process-induced charging damage is studied for metal-oxide-semiconductor (MOS) devices with gate oxide thickness of 1.9–3 nm. It is found that plasma charging damage of ultra thin oxide strongly depends on its initial oxide quality. The ultra thin oxide of around 2 nm thick is not always free from plasma charging damage, if the fabrication process other than the plasma process is not optimized. A mechanism of the enhanced plasma charging damage due to gate electrode formation process is proposed. If defects exist in the oxide, these defects become weak paths for the injected current during the plasma process. Thus, current density at the defects becomes high and oxide breakdown occurs even when the oxide is as thin as 2 nm, in which current conduction by direct tunneling dominates.

Effects of Hydrogen and Deuterium Annealing on Plasma Process Induced Damages

For n-channel metal-oxide semiconductor field effect transistor(MOSFET) devices with thin gate oxide, the effects of low temperature hydrogen and deuterium annealing on plasma process-induced damages are examined. The test devices were first exposed to the plasma during poly-Si gate or metal processes, and then the device characteristics were measured with the charge pumping method. It was observed that the metal process induced more interface traps than the poly-Si gate process. D2 annealing was more effective in curing the interface damages than H2 annealing, and the strength to resist ac electrical stress was enhanced significantly after D2 annealing. The stability of interface properties was increased with the annealing temperature and time. It is concluded that the latent damages, which appear after electrical stress, originate from the plasma process-induced damages that were unintentionally passivated by hydrogen atoms during subsequent processes.

Plasma damage in thin gate MOS dielectrics and its effect on device characteristics and reliability

Plasma process-induced damage continues to be a great threat and concern in the modern CMOS technologies. This article concentrates on NMOS vs. PMOS device sensitivity to plasma charging originating from the various processing steps. This dependence is studied with respect to the gate oxide thickness, and large antenna devices are used to evaluate device yield, latent damage, and residual effect of charging on device performance and reliability. Specific studies are performed to explore the resistance to the charging damage in CMOS devices with a 50 Å gate oxide grown with various oxidation processes.

Scanning tunneling microscopy and spectroscopy characterization of ion-beam-induced dielectric degradation in ultrathin SiO2 films and its thermal recovery process

We have investigated dielectric degradation in ultrathin SiO2 films induced by ion-beam irradiation and its thermal recovery by using scanning tunneling microscopy (STM) and spectroscopy. Our STM results showed that although the ion-beam-induced damage uniformly spreads on the oxide, the dielectric properties are locally recovered by thermal annealing. We found that the tunneling spectra obtained from the ultrathin SiO2 films are sensitive to the process-induced damage, and observed both a leakage current through the damaged oxide film and the thermal recovery of the insulating features. In addition, we confirmed a local charging phenomena of the damaged oxide caused by electron traps around the STM tip.

Metalorganic chemical vapor deposition selective growth and characterization of InGaN quantum dots

InGaN quantum dots (QDs) have been formed by metalorganic chemical vapor deposition selective growth on Si-patterned GaN/sapphire substrates. The QDs were fabricated on GaN plinths grown within nanoscale circular windows opened in the Si mask by both focused ion-beam irradiation and photoassisted wet chemical etching. Using this process, the epitaxial growth of GaN plinths could be achieved on an underlying GaN layer spared from process-induced damage. The optical properties of the InGaN QDs have been investigated by low-temperature cathodoluminescence measurements. Compared to the band-gap emission from a reference sample of InGaN/GaN multiple quantum wells, the evident blueshift of the emission peak from the InGaN QDs was demonstrated. This result suggests that the carriers in the InGaN QDs were three-dimensionally confined.

Plasma process-induced band-gap modifications of a strained SiGe heterostructure

Exposure to plasma etching and subsequent annealing can relax the strain of coherently strained SiGe. This work investigates the change in valence-band discontinuity in plasma-exposed SiGe films due to strain relaxation by a capacitance–voltage (C–V) profiling technique using metal–oxide–semiconductor structures. Dry and wet etched samples annealed at 500, 600, 700, and 800 °C were investigated. Valence-band discontinuity ΔEV at the Si/SiGe interface reduced with annealing temperature and completely disappeared at higher temperature annealing. Dry etched samples demonstrated a faster relaxation mechanism as compared to their wet etched counterparts. The C–V method has turned out to be a simple, fast, and efficient approach to estimate any band-gap modifications in SiGe due to process-induced damage.

The prospect of process-induced charging damage in future thin gate oxides

Abstract Gate oxide scaling effect on plasma charging damage is discussed for various IC fabrication processes such as metal etching, contact oxide etching, high current ion implantation, and via contact sputtering. Capacitance distortion, stress-induced leakage current, MOSFET characteristics, and circuit performance are used for evaluating the charging damage. We observed that very thin gate oxides are less susceptible to the charging damage because of their lower rate of interface damage, larger charge-to-breakdown, and less device determined stress voltage in the plasma system. We also discuss the diode protection scheme and design techniques for minimizing the charging damage. Latent damage exists after thermal annealing and can be revealed during the subsequent device operation causing circuit performance degradation. High density plasma etching is a trend of the etching technology as it provides better anisotropy, selectivity, and uniformity. Its effects on oxide charging damage is compared with low-density plasma etching. The resistance to process-induced charging damage of future devices appears to be high. This is counter-intuitive and is a good tiding for the future of IC manufacturing. The emergence of alternative gate dielectric raises questions about charging damage that requires further studies.

Anomalous junction leakage current induced by STI dislocations and its impact on dynamic random access memory devices

As the density of dynamic random access memory (DRAM) increases up to giga-bit regime, one of the important problems is the control of the process-induced defects and damage. Although the shallow trench isolation (STI) is widely used for deep submicron devices, it has a great possibility of generating STI dislocations due to its inherently large mechanical stress and damage. When STI dislocations are located within the depletion region of pn junction, anomalous junction leakage current could flow. This junction leakage current degrades the memory cell data retention time and the standby current of DRAM. We resolved the problems from STI dislocations as follows; the crystal defects and the mechanical stress were reduced by optimizing the implantation condition and the densification temperature of trench filled high-density plasma (HDP) oxide, respectively. In addition, the residual mechanical stress before source/drain implantation was relieved through rapid thermal nitridation (RTN). By using these methods, STI dislocations were successfully clamped outside the depletion region of pn junction.

Reliability of ultrathin gate oxides for ULSI devices

Abstract Ultrathin gate oxide, which is essential for low supply voltage and high driving capability, is indispensable for the continued scaling of ULSI technologies towards smaller and faster devices. Needless to say, the reliability of ultrathin oxide is of major concerns in the manufacturing of the state-of-the-art metal-oxide-semiconductor devices. This paper reviews the reliability issues regarding ultrathin gate oxide for present and future ULSI technologies. Issues including gate leakage current, time-dependent dielectric breakdown, poly-gate depletion, boron penetration, and plasma process-induced damage will be addressed. Several techniques such as nitrided oxide and alternative processes, which are proposed to improve gate oxide reliabilities, are also discussed.

Surface damage assessment of nanometre finish substrates using differential reflectance spectroscopy

Differential reflectance spectroscopy (DRS) is a comparative technique that measures the normalized difference in reflectivity between samples in the UV to near IR region of the spectrum. We apply the technique to gallium arsenide substrates that have undergone different processing treatment. Spectral features are observed that can be assigned to critical point energies of the band structure. It is suggested that these features arise from strain in the crystal lattice and that DRS is a possible candidate for monitoring process-induced damage in substrate preparation.

A new simulation model for plasma ashing process-induced oxide degradation in MOSFET

Plasma ashing process-induced oxide damage is studied quantitatively in this paper. To simulate thin gate-oxide damage due to the plasma ashing process, a new equivalent circuit model is proposed by including a differential capacitance, a parasitic resistance, an offset flatband voltage, and the effects of feedback on the interface-state and trapped oxide charge densities generated during the plasma ashing process. According to this new model, computation of gate oxide charging current is performed by correlating to the latent interface-state density. The test n-MOSFET devices, including different antenna-ratios are measured, and excellent agreement is obtained as compared with measured results. Moreover, the deficiency of the previous model is stated and compared. In addition, the effects of substrate doping concentration on plasma-induced oxide damage are also investigated as well as those of plasma ion density, plasma uniformity, thin gate-oxide thickness. Therefore, the relationships between interface states/oxide traps and antenna ratio are linked to provide a guideline for circuit designers and the plasma ashing process-induced damage can be predicted.

Machining and surface integrity of fibre-reinforced plastic composites

The current focus of manufacturing research on fibre-reinforced plastics (FRP) is composed of the search for efficient processing techniques capable of providing high quality machined surfaces. Very limited work has been performed to identify the influence of manufacturing processes like edge-trimming and drilling on material performance. Recent reports suggest that process-induced damage may affect the mechanical behaviour of FRP materials. Therefore an experimental study of orthogonal cutting was conducted on the edge trimming of unidirectional and multi-directional graphite/epoxy composites with polycrystalline diamond tools. The effects of tool geometry and operating conditions were evaluated from an analysis of chip formation, cutting force, and machined surface topography. All aspects of material removal were found to be primarily dependent on fibre orientation. Discontinuous chip formation was noted throughout this study, regardless of machining parameters. Three distinct mechanisms in the edge trimming of fibre-reinforced composite material including a combination of cutting, shearing, and fracture along the fibre/matrix interface were observed. An investigation conducted on the compression, flexural and impact strength of graphite/epoxy composites machined by both traditional and non-traditional techniques, confirms that manufacturing characteristics may not only affect bulk properties but also influence the initiation and propagation of failure.

Comparison between direct current and sinusoidal current stressing of gate oxides and oxide/silicon interfaces in metal–oxide–silicon field-effect transistors

It was recently reported that plasma process-induced damage to metal–oxide–silicon field-effect transistors (MOSFETs) comprises a damage mechanism that involves alternating-current (ac) stressing of the oxide and the oxide/silicon interface. The study reported herein is aimed at establishing signatures of MOSFET damage induced by ac stressing applied at conditions that emulate plasma processing environment. We apply sinusoidal ac voltage stress signals to 0.5 μm n-channel or p-channel MOSFETs with 90-Å-thick gate oxides. We assess damage on MOSFETs by measuring transconductance, threshold voltage, and subthreshold swing. We find that the onset of damage to devices subjected to ac stressing occurs at voltage amplitudes as low as 4 V, whereas in dc stressing, applied for the same time, damage becomes significant only at dc voltages larger than 10 V. We also show that damage from ac stressing attains a maximum at frequencies in the range 1–100 kHz and decreases at frequencies above 5 MHz. It is proposed that carrier hopping is primarily responsible for oxide current and, hence, device damage observed following the ac stress. This hopping current is insignificant during high-field dc stress when Fowler–Nordheim tunneling becomes the dominant conduction mechanism.

Simulating process-induced gate oxide damage in circuits

Advanced processing techniques such as plasma etching and ion implantation can damage the gate oxides of MOS devices and thus pose a problem to circuit reliability. In this paper, we present a simulator which predicts oxide failure rates during and after processing and pinpoints strong charging current locations in the layout where changes can be made to improve circuit hot-carrier reliability. We present the models and experimental results used to develop the simulator and demonstrate the usefulness of this simulator.

A full-process damage detection method using small MOSFET and protection diode

Short constant voltage stress was applied to the gate of triple metal process transistors to uncover otherwise undetectable process-induced damage, 1 s at 9 MV/cm was enough to distinguish the damaged devices from the undamaged ones clearly in the transistor characteristics. The process damage was detected even after forming gas anneal and without using large antenna test structures to gather the charges. Also, the small diode provided a good leakage path to protect the gate from plasma process induced charging even in the reverse polarity. Diode-protected devices can be used as references in this damage detection scheme.

Simple method for evaluating process-induced charging damage to the gate oxide of metal-oxide-semiconductor devices

This letter presents a simple approach to characterize process-induced charging damage in the gate oxide of metal-oxide-semiconductor (MOS) devices. The method uses the monitoring of voltage transients during constant-current stress performed on plasma-damaged and reference devices. The difference in transients allows direct extraction of the amount of electron traps created in the oxide by charging currents during processing. The method is verified by experimental simulation and applied to extract the density of electron traps introduced in the oxide by process-induced charging. This technique is a fast and efficient approach to assess device damage and extract physical parameters of generated traps which can be used later for lifetime prediction in reliability simulators.

Hole trap generation in the gate oxide due to plasma-induced charging

The paper presents results of hole trapping studies in-thin gate oxide of plasma damaged MOS transistors. Process-induced damage was investigated with antenna test structures to enhance the effect of plasma charging. In addition to neutral electron traps and passivated interface damage, which are commonly observed plasma charging latent damage, we observed and identified hole traps, generated by plasma stress. The amount of hole traps increases with increasing antenna ratio, indicating that the mechanism of hole trap generation is based on electrical stress and current flow, forced through the oxide during plasma etching. The density of hole traps in the most damaged devices was found to be larger than that in reference, undamaged devices by about 100%.

Pattern transfer and photoluminescence damage assessment of deep-submicrometer features etched by photon-induced cryoetching

We present a study of pattern-transfer and etch-induced damage in photon-induced cryoetching. Features with effective radii as small as ≈ 100 nm have been formed in both bulk and layered GaAs/AlGaAs materials. A measurement of the photoluminescence of etch-defined deep- submicrometer structures material suggests that this form of etching results in minimal process-induced damage. Modeling of the luminescence vs feature size for these features shows that the luminescence is limited only by carrier diffusion and non-radiative surface recombination.

Modulation Spectroscopy of Reduced Dimensional Semiconductor Systems

This paper reviews the background of modulation spectroscopy, particularl yelect onnodulation, presents some recent room temperature results hav-ing both fundamental and technological significance, including two-dimensional electron gas echects in modulation-doped, pseudomorphic GaAlAs/InGaAs/GaAs single quantum wells (HEΜΤ structures), quantum well laser structures and process-induced damage in quantum dot arrays fabricated by reactive ion etching. PACS numbers: 78.66.—w, 78.66.Fd, 78.40.Fy