Process-induced Damage Research Articles

Threshold Voltage Instability Induced by Plasma Process Damage in Advanced Metal–Oxide–Semiconductor Field-Effect Transistors

The effects of plasma process-induced physical damage on n-channel metal–oxide–semiconductor field-effect transistor (MOSFET) performance were investigated in detail in terms of threshold voltage (Vth) and Vth shift (ΔVth). The Si recess structure formed by ion bombardment was primarily focused on in this study. Defect site density was also considered as a possible cause of ΔVth. The damaged structure and damage formation mechanisms were studied using an optical analysis technique and classical molecular dynamics simulations. The plasma-induced ΔVth of devices with various recess depths was estimated by technology computer-aided design (TCAD) simulations, by taking into account the bias power dependence of damaged layer thickness. The Vth related to the recess structure shifts toward the negative direction in n-channel MOSFETs, indicating an increase in off-state leakage current (IOFF). |ΔVth| proportionally increases with the increasing recess depth dR (∼ bias power), while the underlying defect density does not affect ΔVth. Moreover, the predicted Vth decrease (ΔVth<0) with an increase in dR strongly depends on gate length (Lg), i.e., the decrement in Vth is inversely proportional to Lg. This suggests that the dR increase induces an exponential increase in the standby power consumption of advanced devices. We provide a comprehensive relationship between device parameters (Vth, Ioff, and Lg) and process parameters for plasma-damaged devices.

Modeling Process-Induced Cell Damage in the Biodispensing Process

Emerging biomanufacturing processes involve incorporation of living cells into various processes and systems by employing different cell manipulation techniques. Among them, biodispensing, in which the cell suspension is extruded via a fine needle under pressurized air, is a promising technique because of its high efficiency. Cells in this process are continually subjected to mechanical forces and may be damaged if the force or manipulation time exceeds certain levels. Modeling cell injury incurred in these processes is lacking in the literature. This article presents a method to quantify the force-induced cell damage in the biodispensing process. This method consists of two steps: first is to establish cell damage laws to relate cell damage to hydrostatic pressure/shear stress; and the second is to represent the process-induced forces experienced by cells during the biodispensing process and apply the established cell damage law to represent the percentage of cell damage. Schwann cells and 3T3 fibroblasts were used to validate the model and the comparisons of experimental and simulation results show the effectiveness of the method presented in this article.

On the fatigue crack growth–microstructure relationship in ultrafine-grained interstitial-free steel

The crack growth behavior in an ultrafine-grained (UFG) interstitial-free (IF) steel processed by equal channel angular pressing (ECAP) was investigated utilizing miniaturized compact-tension specimens with different microstructural characteristics. The current results demonstrate that both the ECAP processing route and the direction of crack growth with respect to the extrusion direction dictate the crack growth behavior in UFG IF steel. Specifically, the highest crack growth rates and the lowest threshold values were observed for the lowest grain size. Moreover, an unusual deviation from the expected direction of crack expansion was observed, where the deviation depended on the processing route and direction of crack growth. This deviation is attributed to the presence of elongated structures in the microstructure, which were mainly detectable in the UFG IF steel following a small number of pressings, and to a smaller extent in the optimized microstructures. Specifically, these elongated structures formed parallel to the material’s plastic flow during ECAP processing and moved the crack away from the expected direction of growth due to the high stress concentration zones they created along with the process-induced damages.

Ultralow-k / Cu Damascene Multilevel Interconnects Using High Porosity and High Modulus Self-Assembled Porous Silica

We introduced a high porosity ultralow- film into a Cu damascene interconnect without increasing the dielectric constant of a low- film after interconnect formation. A high elastic modulus (9 GPa) with ultralow- value was achieved by using a self-assembled porous silica film formed with UV irradiation and a silylation anneal. Performing the silylation anneal after trench etching results in recovery of the value and dielectric properties. A sidewall protection process carried out before metalization protects the low- film against process-induced damage. The time-dependent-dielectric breakdown lifetime is 10 years at a high electric field of 2.3 MV/cm.

Surface Texturing of Tribological Interfaces Using the Vibromechanical Texturing Method

Modifying the surface topography of tribological interfaces has the potential to improve the friction performance of certain mechanical components that experience sliding contact. Vibromechanical texturing (VMT), an improved texturing method based on the convenient turning process, is introduced. This process is performed on a standard computer numeric controlled (CNC) lathe, which is retrofitted with a piezoelectric-actuated tool positioning stage. Controlled vibratory motion of the tool is used to cut microsized dimples into the surface of the workpiece. Two types of workpiece materials are used: aluminum and hardened steel, with three forms of workpiece geometries: outer cylinder, inner cylinder, and flat/end face. The accuracy of the texturing method is compared with a basic surface topography model, which predicts texture dimensions within an 11% error for aluminum and up to 90% error for hardened steel, using the current open-loop control system. Further analysis of the textured samples shows no significant signs of process-induced damage. It is demonstrated that this VMT method is a versatile, accurate technique that has potential to be a cost-effective means for surface texturing of tribological components.

Integration of Self-Assembled Porous Silica in Low-k/Cu Damascene Interconnects

Integration of a self-assembled porous silica film layered with a cap film was carried out for low-k/Cu damascene structures. The dielectric constant of the porous silica in the layered damascene structure was extracted, and the process-induced damage layer was characterized. Due to the integration process of low-k/Cu damascene, the hydrophobic methyl group was decomposed by plasma etching and subsequent barrier and seed sputtering as well as by Cu electroplating, resulting in the formation of hydrophilic silanol groups. The lateral dimension of the process-induced damaged layer and its effective dielectric constant were found to be 35 nm and 10, respectively.

Transparent dual-gate InGaZnO thin film transistors: OR gate operation

Transparent dual-gate (DG) InGaZnO4 thin film transistors for OR logic operation were fabricated on a glass substrate. A 100-nm-thick SiO2 layer used as both top and bottom gate dielectrics was deposited by plasma enhance chemical vapor deposition at 200°C. Compared to bottom gate, top gate thin film transistors (TFTs) exhibited better device performance with higher saturation mobility, drain current on-to-off ratio, lower threshold voltage, and subthreshold gate-voltage swing. This improved performance was mainly attributed to low process-induced damage or low parasitic capacitance between gate and source/drain and low parasitic resistance between channel and source/drain in top-contact TFT configuration (coplanar type). DG-mode TFTs showed saturation mobility of ∼16.9cm2V−1s−1, drain current on-to-off ratio of ∼1×106, subthreshold gate-voltage swing of ∼0.33Vdecade−1, and threshold voltage of ∼1.25V. The results demonstrate that DG InGaZnO4 TFTs are effective in improving the device performance because the channel layer is modulated independently by a top or, bottom gate signal and are well suited for OR gate operation.

Effect of laser fluence on yeast cell viability in laser-assisted cell transfer

Matrix-assisted pulsed-laser evaporation direct-write (MAPLE DW) has been emerging as a promising biological construct fabrication technique. The post-transfer cell viability in MAPLE DW depends on various operation conditions such as the applied laser fluence; unfortunately, the effect of laser fluence on the post-transfer cell viability has not been well elucidated. This work aims to study the effect of laser fluence on the post-transfer cell viability and the cell recovery ability in MAPLE DW of yeast cells (Saccharomyces cerevisiae). It has been observed that (1) yeast cell viability decreases as the laser fluence increases from 85 to around 1500mJ∕cm2 and (2) some of the MAPLE DW process-induced cell damage is reversible. The post-transfer yeast cell recovery is a function of laser fluence; however, this dependence relationship is not monotonic. Future work is needed to better understand the physical and chemical mechanisms of the above observations.

Statistical Characterization of Process-Induced Plasma Damage

During plasma processes, charging damage produces various defects in silicon oxide, thereby deteriorating device performance. Optimizing process-induced charging damage requires a computer model, as well as a quantitative analysis of process parameter effects. In this study, plasma charge damage on threshold voltage of metal-semiconductor field-effect transistors is statistically investigated. This includes the analysis of main and interaction effects of process parameters, as well as the construction of response surface models. Charging damage is characterized by means of a statistical experiment. Four types of statistical regression models are constructed. A model with the largest R-Square (R2) fit of 90.6 is chosen for the response surface analysis. Analysis of the main effects revealed that radio frequency power and gas ratio are the most significant and least significant factors, respectively. Among various interaction terms, only the interaction between radio frequency power and bias is found to be influential. Meanwhile, several conflicting effects are noted as the bias power or gas ratio are varied. An optimized regression model is used to understand parameter effects on plasma charging damage.

Experimental Investigation on the Process-Induced Damage of a Direct Methanol Fuel Cell Assembled by the Printed Circuit Board Technique

The printed circuit board (PCB)-based direct methanol fuel cell (DMFC) package is a novel manufacturing and assembly process, which is full potential in mass production, and very limited literatures make study on the effects of the related process parameters. The hot press is a necessary and key process to make the PCB package, i.e., the key component of a DMFC, membrane electrode assemblies (MEA), needs to sustain a severe test. In order to minimize the process-induced damage of the MEAs, it is important to make a good control on the process parameters. Therefore, the objective of this paper is to present a methodology to explore a good combination of hot-press parameters. The considered parameters include the compression ratio of the MEA, heating time, heating temperature, and hot pressing pressure acting on the MEA. During the experimental investigation, a series of experiments was made first to discuss the effect of the individual parameter of the hot-press process on the MEA performance, wherein a reasonable range of each process parameter condition was able to be well defined. Moreover, the Taguchi experimental method was adopted to explore the parameter effects on the DMFC performance during the digital packaging process and to determine the best combination of parameter conditions. At the end, a MEA was made a hot press under the best parameter combination, which could verify the result obtained from Taguchi’s experiments. The result is able to be an important reference for the future manufacturing design guideline of PCB-based DMFC package.

Comprehensive Chemistry Designs in Porous SiOCH Film Stacks and Plasma Etching Gases for Damageless Cu Interconnects in Advanced ULSI Devices

High performance Cu dual-damascene (DD) interconnects without process-induced damages are developed in porous SiOCH stacks with the effective dielectric constant (k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ) of 2.95, in which a carbon (C)-rich molecular-pore-stacking (MPS) SiOCH film (k = 2.5) is stacked directly on an oxygen (O)-rich porous SiOCH (k = 2.7) film. The novel etch-stopperless structure is obtained by comprehensive chemistry design of C/O ratios in the SiOCH stack and the etching plasma of an Ar/N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /CF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> /O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gas mixture technique. Large hydrocarbons attached to hexagonal silica backbones in the MPS-SiOCH prevent the Si-CHx bonds from oxidation during O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -plasma ashing, suppressing the C-de- pleted damage area at the DD sidewall. Combining multiresist mask process with immersion ArF photolithography, strictly controlled Cu DD interconnects with 180-nm pitched lines and 65-nm-diameter vias are obtained successfully, ready for the 300-mm fabrication.

Impact of Barrier Metal Sputtering on Physical and Chemical Damages in Low-k SiOCH Films with Various Hydrocarbon Content

Impact of barrier metal sputtering on physical and chemical damages in the low-k SiOCH films is investigated. In RF sputtering system, the potential drop across the anode sheath accelerates the ion in the plasma toward the wafer surface, inducing damages in the low-k SiOCH dielectrics. High DC bias on the target reduces the anode sheath voltage to suppress the process-induced damage in the SiOCH films. For conventional rigid and porous SiOCH films with methyl (–CH3) additives, the accelerated ions break the Si–CH3 bond, pushing up the dielectric constants. A new type of SiOCH film such as a molecular-pore-stacking (MPS) SiOCH, which is consisted of hexagonal silica ring with a large amount of hydrocarbon groups surrounding the core silica structure, exhibits high endurance to the sputtering-induced damages. The long side-chains of the hydrocarbon prevent the direct ion bonberdment to the core Si–CH3 bonds by sacrificing the C–C bond in the chains, keeping the low dielectric constant in the MPS SiOCH.

Quantitative and comparative characterizations of plasma process-induced damage in advanced metal-oxide-semiconductor devices

Two plasma process-induced damage mechanisms are investigated in detail: charging damage by plasma conduction current through two different gate dielectrics (SiO2 and HfAlOx/SiO2 (high-k)) in metal-oxide semiconductor (MOS) devices and ion-bombardment damage in Si surfaces. The charging damage was identified as the changes in tunnelling currents and the decrease in the reliability lifetime. The behaviours were found to depend on the dielectric thickness as well as dielectric materials (SiO2 and high-k). For p-ch MOS transistors, the threshold voltage of devices with high-k exposed to Ar-based plasma shifted towards the positive direction, while with SiO2, towards the negative direction. This may be attributed to the difference in the trap site generation process and trapping phenomenon. With regard to the ion-bombardment damage, the changes in optical structures (surface layer thicknesses, dielectric function and mechanical strain within the interfacial damaged layers) by direct current and electron cyclotron resonance plasma exposures were investigated by spectroscopic ellipsometry and photoreflectance spectroscopy. The plasma-induced stressing current and the defect density were estimated to quantify the damage. The experimental findings provide key implications that a plasma-induced damage is one of the limiting factors for future-scaled device designs.

Effects of Dispensing Pressure and Nozzle Diameter on Cell Survival from Solid Freeform Fabrication–Based Direct Cell Writing

Novel technologies are emerging that incorporate cells as part of the building blocks for various biomanufacturing processes, such as solid freeform fabricated tissue constructs for tissue regeneration, three-dimensional pharmacokinetic models, cell-based microelectromechanical systems, sensors, and microfluidic devices. However, the effects of these biomanufacturing processes on cells have not been fully studied. This paper examines the effect of solid freeform fabrication-based direct cell writing process, focusing on dispensing pressure and nozzle size, on the viability and functional behavior of HepG2 cells encapsulated within alginate. Our experimental results revealed a process-induced mechanical damage to cell membrane integrity, causing a quantifiable loss in cell viability due to incremental increases and decreases in the studied process parameters of dispensing pressure and nozzle size, respectively. The experimental results also suggested that cells may require a recovery period following direct cell writing biofabrication. The general finding of this study may be applicable to freeform fabrication of cell-based tissue constructs and three-dimensional biological models.

Plasma process-induced damage to Josephson tunnel junctions in superconductingintegrated circuits

It has been found that the critical current of Josephson junctions in superconductingintegrated circuits may depend on the environment surrounding the junctions and on how aparticular junction is connected (wired) to other junctions and circuit elements. This maycause large, pattern-dependent deviations of the junctions’ critical currents from designvalues and ultimately limit the yield and performance of superconducting digital integratedcircuits. In particular, we have found a difference in the critical current of grounded andfloating junctions, and a dependence of the critical current on the size of metal structuresconnected to the junction—the ‘antenna’ effect. Experimental data were obtained forNb/AlOx/Nb Josephson junctions fabricated on 150 mm wafers by an 11-layer process for superconductingintegrated circuits. The results are explained by plasma process-induced damage toultra-thin tunnel barriers. The most damaging plasma processing fabrication steps arediscussed.

Optically Controlled Silicon MESFET Modeling Considering Diffusion Process

An analytical model is proposed for an optically controlled Metal Semiconductor Field Effect Transistor (MESFET), known as Optical Field Effect Transistor (OPFET) considering the diffusion fabrication process. The electrical parameters such as threshold voltage, drain-source current, gate capacitances and switching response have been determined for the dark and various illuminated conditions. The Photovoltaic effect due to photogenerated carriers under illumination is shown to modulate the channel cross-section, which in turn significantly changes the threshold voltage, drainsource current, the gate capacitances and the device switching speed. The threshold voltage VT is reduced under optical illumination condition, which leads the device to change the device property from enhancement mode to depletion mode depending on photon impurity flux density. The resulting I-V characteristics show that the drain-source current IDS for different gate-source voltage Vgs is significantly increased with optical illumination for photon flux densities of Φ = 10 15 and 10 17 /㎠s compared to the dark condition. Further more, the drain-source current as a function of drain-source voltage VDS is evaluated to find the I-V characteristics for various pinch-off voltages V P for optimization of impurity flux density QDiff by diffusion process. The resulting I-V characteristics also show that the diffusion process introduces less process-induced damage compared to ion implantation, which suffers from current reduction due to a large number of defects introduced by the ion implantation process. Further the results show significant increase in gate-source capacitance C gs and gate-drain capacitance C gd for optical illuminations, where the photo-induced voltage has a significant role on gate capacitances. The switching time τ of the OPFET device is computed for dark and illumination conditions. The switching time τ is greatly reduced by optical illumination and is also a function of device active layer thickness and corresponding impurity flux density Q Diff . Thus it is shown that the diffusion process shows great potential for improvement of optoelectronic devices in quantum efficiency and other performance areas.

Threshold Voltage Shift Due to Mechanical Stress-Enhanced Plasma Process-Induced Damage in 0.13-$\mu\hbox{m}$ pMOSFET

Mechanical stress-enhanced plasma process-induced damage (PPID) in 0.13-mum pMOSFET was investigated. The PPID, which was initially charged neutral, became positively charged during hydrogen annealing, thus, changing the PMOS threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ). Different device structures were designed to evaluate the mechanical stress effects on PPID. The features of these positive charges, including the PPID induced V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift, and its channel length dependence were also investigated

Introduction to the Special Issue on the 2006 International Reliability Physics Symposium

The 12 papers in this special issue are extensions of presentations given at the 44th Annual IEEE International Reliability Physics Symposium (IRPS), held in San Jose, CA, on March 26-30, 2006. The diverse set of papers include studies in assembly and packaging reliability, interconnect reliability, latchup, product reliability, soft error rate, memory reliability, process-induced damage, and transistor reliability. The papers are briefly summarized here.

Reduction of Process-induced Damage and Improvement of Imprint Characteristics in SrBi2Ta2O9 Capacitors by Postmetallization Annealing

We investigated the effect of process damage induced after capacitor etching procedures in the process of ferroelectric random access memory (FeRAM) fabrication for SrBi2Ta2O9 capacitors. We found that this damage was suppressed by postmetallization annealing (400 °C, 30 min in O2) and that imprint characteristics were improved by the annealing, because active elements such as hydrogen and water induced during contact hole formation on tungsten plugs and first-metal formation are adsorbed effectively by the annealing before they penetrate into these capacitors.

Effects of Storage Conditions on Imprint Characteristics in SrBi2Ta2O9 Capacitors

The effects on the imprint characteristics of SrBi2Ta2O9 capacitors of various storage conditions were investigated. It was observed that the hysteresis shifts due to imprint degradations were smaller in the case in which the both electrodes of the capacitors were connected after increasing the temperature of the capacitors that were polarized at room temperature than in the case in which the electrodes were not connected. The acceleration ratio (Racc) of the slope of the hysteresis shift in the capacitors without connected electrodes to that with connected electrodes is 1.35 at 125 °C in device-size capacitors, and the ratio is much less dependent on temperature than the hysteresis shift. Moreover, it was also found that Racc was smaller in the case in which the process-induced damage located near the interfaces was larger.