Selective epitaxy is a process used in a wide range of applications such as in Heterojunction Bipolar Transistors (HBT) [1] Raised Sources and Drains (RSDs) for n-type Field Effect Transistors (fin-FETs) [2], p-type Metal Oxide Semiconductor Field Effect Transistors (pMOSFETs) [3] or III-V-on-Si heteroepitaxy for optoelectronic devices [4] ...Standard selective epitaxial growth, called co-flow process, requires Cl, provided by HCl, to etch poly/amorphous nuclei on the dielectric during the growth, allowing for deposition restricted to areas not covered by a dielectric. For the development of advanced technologies, out-of thermal equilibrium conditions (typically < 600 °C) are required for high germanium contents (> 50%), high substitutional carbon concentrations (> 1 at%) and high active doping levels (> 1x1020 at.cm3) while complying with thermal budget limitations. The co-flow processes results in deposition on the dielectric mask at these low growth temperatures and needs to be replaced by Cyclic Deposition Etch (CDE) processes, alternating between non-selective deposition and etch. These CDE processes are commonly used to reach selectivity at low growth temperatures for SiC:P [5] and tensile-strained Si:P layers [2]. The present study investigated the feasibility of selective epitaxial growth of thin SiGeC:B layers on patterned wafers using a CDE process or a single deposition etch process (DE).The SiGeC:B epitaxial growth behaviors using the Si2H6/GeH4/SiH3CH3/B2H6 chemistry at 550 °C, 10 Torr, were investigated for various SiH3CH3 flow ratios on blanket Si wafers. Under the present experimental conditions, the Ge content and B concentration were 25% and 1x1020 at.cm-3, respectively. XPS measurements showed (Fig1.a) that the C 1s signal intensity increased proportionally with the SiH3CH3 flow, without any shift in the binding energy (here, 284.05 eV for the substitutional carbon) or broadening of the C 1s signal. The interstitial component, systematically included in the XPS fitting procedure, is located at 0.70 eV lower than the substitutional component. The interstitial C concentrations were constant and virtually close to zero (below 0.1 at% which is the XPS detection limit). Carbon atoms (for both SiGeC and SiGeC:B) were therefore only incorporated into substitutional sites, with concentrations up to ~ 1.4 at% (Fig1.b).To achieve selective growth on patterned wafers, two different approaches were evaluated on blanket Si substrate and blanket Si covered with 10 nm of Si3N4.An isothermal CDE process with 10 cycles at 550°C for both the deposition and etch step at 10 or 50 Torr with a total deposition time of 100 s (10*10s/cycle) was investigated. F(HCl)/F(H2) flow ratio was set to 1.7. Fig2.a) shows the monocrystalline SiGeC:B layer thickness (on a blanket Si wafer) and the poly-SiGeC:B layer thickness (on Si3N4) as a function of the total HCl time. This CDE process resulted in rather low etch rates, equal to 1.6 and 2.8 nm.min-1 for c-SiGeC:B and poly-SiGeC:B, respectively. The etch selectivity (defined as the poly-etch rate divided by the c-etch rate) was around 1.8. The “apparent” Ge concentration, measured by XRD, increased from 12.5% (no HCl etch) to 16.8% with the HCl etch duration. The layers also became rougher as the etching time increases.To overcome the limitations of the CDE process, deposition / etch processes with only one etch step operating at 600 Torr, with a HCl flow ratio of 0.17 were investigated at 550°C, 575°C and 600°C (Fig2.b). Increasing the temperature led to an increase of both the c-SiGeC:B and poly-SiGeC:B etch rates with similar activation energies of 1.92 and 1.99 eV, respectively. Therefore, the etch selectivity of 1.8, in this study, was temperature independent. Using a DE approach, the “apparent” Ge remained constant, independent of the HCl etch duration. A slight surface roughening was however also observed as the etch time increases.The processes were transferred to patterned wafers by adjusting the deposition time (8 s/cycle and 55 s in total for the CDE and DE process, respectively) based on Fig2. The CDE and DE processes both resulted in selective epitaxial growth on a Si3N4 surface (Fig3). However, the layer grown by the CDE approach was more defective (Fig.3a)) whereas a rather smooth layer was obtained using the DE process (Fig.3b)).It was shown that the use of a CDE process is not a viable solution for achieving high quality SiGeC:B films on patterned wafers, while the DE approach resulted in a more promising quality of SiGeC:B.[1] P.Chevalier, IEEE International Electron Devices Meeting 3.9.1-3.9.3 (2014)[2] J.M.Hartmann, ECS Transactions, 109 (4) 99-120 (2022)[3] J.Aubin, Semicond. Sci. Technol. 30 (2015)[4] J.S.Park, Crystals, 10, 1163, (2020)[5] M.Bauer, ECS Transactions, 3 (7) 187-196 (2006) Figure 1
Read full abstract
Jan 14, 2025
Sławomir Winiarski + 2
Just Published
Open Access