Printed Wiring Board Assembly Research Articles

Large Form Factor Hybrid LGA Interconnects; Recent Applications and Technical Learning

Recent high-end server design trends have continued to challenge electronic packaging engineers to design and integrate larger form factor land grid array (LGA) attached modules within their assemblies. These trends have included the application of larger, denser, organic packaged modules whose electrical performance and postencapsulation physical characteristics have been enabled by both the continued development of hybrid LGA connectors as well as new module actuation hardware designs. In this paper, we'll discuss these recent trends, including the specific technical attributes and challenges that need to be addressed to ensure a repeatable and reliable assembly design is developed. Initially, overviews of the latest connector and module design trends, including styles and physical sizes and their implications to the module's bottom surface metallurgy (BSM) flatness requirements, etc. are provided. Pursuant to this, recent system integration trending is reviewed; including both the module quantity per system assembly as well as module to module physical placements and how each of these impact printed wiring board (PWB) design (i.e., layer count, LGA site flatness, etc.) as well as the PWB assembly's solder processing characteristics (i.e., LGA pre- and post-solder attach contact co-planarity, etc.). Completing the application portion, is a description of some recent LGA actuation hardware and module external cooling apparatus designs (e.g., air-cooled heats sinks and water-cooling cold-plates and thermal interface materials (TIMs), etc.). The remaining portion of the paper is dedicated to the description of the mechanical analysis efforts completed to provide a fundamental understanding of the design's “as-assembled” attributes and a review of the associated evaluation completed to verify the integrated assembly's reliability characteristics. From the analysis methodology perspective, both the means of including each of the integrated assembly's key attributes (e.g., module mechanical construction and as encapsulated flatness, LGA contact compliance and stiffness as well as soldered contact coplanarity, TIM stiffness, actuation hardware, heat sink and cold-plate mechanical construction, etc.) and the resulting estimation of the predicted module internal TIM and hybrid-LGA's Pb-free soldered interface strains, actuation hardware stresses and LGA contact load variation are provided. Completing the discussion is a review of the variety of testing executed to validate the design's intended reliability. Included in this is a description of the test vehicle's design, the environmental stress testing conducted (i.e., mechanical pre-conditioning, accelerated thermal cycling (ATC), mixed flowing gas (MFG) and heat aging (HA), etc.) and the resulting data.

Techniques for Measuring Warpage of Chip Packages, PWBs, and PWB Assemblies

One of the crucial factors for the thermo-mechanical reliability of electronic packages is warpage that occurs during the printed wiring board (PWB) fabrication, solder masking and solder reflow processes. As the quality and reliability requirements of electronic components (packages) become higher, warpage control becomes a more crucial process during the PWB fabrication (manufacturing) and package assembly processes. The warpage of PWBs, PWB assemblies and electronic packages are measured by various techniques. Each technique has both its advantages and disadvantages; therefore the choice of a particular technique depends on whether one wants to measure the warpage of a PWB, PWB assembly or chip package. This paper reviews the pros and cons, such as resolution, speed, costs, accuracy, in-line capability, flexibility, and robustness, of different techniques used for measuring the warpage of chip packages, PWBs and PWB assemblies.

3D Integration of System-in-Package (SiP): Toward SiP-Interposer-SiP for High-End Electronics

The demand for high-performance, lightweight, portable computing power is driving the industry toward 3D integration to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate multiple substrates, multiple dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. The approaches explored in this paper include eliminating active chip packages by directly attaching the chip to the System-in-Package (SiP) with flip chip technology. Additionally, the area devoted to passive components can be greatly reduced by embedding many of the capacitors and resistors. In some instances, the connector systems that were consuming large amounts of space in the traditional Printed Wiring Board (PWB) assembly can be reduced with a small pitch connector system. This PWB assembly can then be transformed into a much smaller SiP with the full surface area on both sides of the package effectively utilized by active and passive components. The miniaturized SiP with its reduced package size and demand for passives requires a high wireability package with embedded passives and excellent communication from top to bottom. In the present study, we also report novel 3D “Package Interposer Package” (PIP) solution for combining multiple SiP substrates into a single package. A variety of interposer structures were used to fabricate SiP-Interposer-SiP modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 m to 250 m, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP solutions on various SiP configurations.

3D Integration of System-in-Package (SiP) Using Organic Interposer: Toward SiP-Interposer-SiP for High-End Electronics

The demand for high-performance, lightweight, portable computing power is driving the industry toward 3D integration to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate multiple substrates, multiple dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. The approaches explored in this paper include eliminating active chip packages by directly attaching the chip to the System-in-Package (SiP) with flip chip technology. Additionally, the area devoted to passive components can be greatly reduced by embedding many of the capacitors and resistors. In some instances, the connector systems that were consuming large amounts of space in the traditional Printed Wiring Board (PWB) assembly can be reduced with a small pitch connector system. This PWB assembly can then be transformed into a much smaller SiP with the full surface area on both sides of the package effectively utilized by active and passive components. The miniaturized SiP with its reduced package size and embedded passives provides a high wireability package with excellent communication from top to bottom. In the present study, we also report a novel 3D “Package-Interposer-Package” (PIP) solution for combining multiple SiP substrates into a single package. A variety of interposer structures were used to fabricate SiP-Interposer-SiP modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 μm to 250 μm, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP solutions incorporating various SiP configurations.

Application of Lamination Theory to Study Warpage Across PWB and PWBA During Convective Reflow Process

Out-of-plane displacement (warpage) has been a major reliability concern for board-level electronic packaging. Printed wiring board (PWB) and component warpage results principally from coefficient of thermal expansion (CTE) mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount assembly processes and normal operations may lead to severe solder bump failures. In this paper, the classical laminated plate theory was applied to study the warpage behavior of PWBs and PWBAs during the thermal reflow process. The rule of mixtures was used to estimate the effective material properties of PWBA composites. Closed form solutions of the differential equations for the PWB and PWBA deformation were generated from the classical lamination theory to evaluate the sample warpage. The board support conditions and thermal gradients through the assembly thickness were considered in the theoretical model. The calculated warpage results were compared with experimental results using the projection moiré measurement system in a simulated convective reflow process to evaluate the accuracy of the model. Finite element modeling was applied to estimate the sample warpage values under the same thermal loading and boundary constraints. The warpage values obtained from the theoretical models show high sensitivity to the thermal loads, through-the-thickness temperature gradients of the test samples, and CTE values of the composite materials. The relative warpage results obtained from the theoretical models and numerical models agreed well with the experimental measurement results during the thermal reflow process.

Effects of Warpage on Fatigue Reliability of Solder Bumps: Experimental and Analytical Studies

Out-of-plane displacement (warpage) has been a major thermomechanical reliability concern for board-level electronic packages. Printed wiring board (PWB) and component warpage results principally from coefficient of thermal expansion mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount assembly reflow processes and normal operations may lead to severe solder bump reliability problems. In this research, the effect of initial PWB warpage on the low cycle thermal fatigue reliability of the solder bumps in plastic ball grid array (PBGA) packages was studied using experimental and analytical methods. A real-time projection moire? warpage measurement system was used to measure the surface topology of PWBA samples at different temperatures. The thermal fatigue reliability of solder bumps was evaluated from experimental thermal cycling tests and finite element simulation results. Three-dimensional (3-D) models of PWBAs with varying board warpage were used to estimate the solder bump fatigue life for different types of PBGAs mounted on PWBs. In order to improve the accuracy of FE results, the projection moire? method was used to measure the initial warpage of PWBs, and this warpage was used as a geometric input to the finite element method. The simulation results were validated and correlated with the experimental results obtained using the projection moire? technique and accelerated thermal cycling tests. An advanced prediction model was generated to predict board level solder bump fatigue life based on the initial PWB warpage, package dimensions and locations, and solder bump materials.

A test-rework process yield performance model for estimation of printed wiring board assembly cost

This paper proposes a new test-rework process yield performance (TRePYP) model, combined with an assembly cost estimation algorithm, for an accurate representation of current practice in printed wiring board (PWB) assembly, especially in the design phase. The model captures the “dedicated” feature of PWB assembly activities and, instead of adopting lumped parameters, utilizes easy-to-measure process parameters so that both assembly performance and assembly cost can be evaluated. In the case study, changes in assembly cost due to lead-free conversion are estimated. Care is taken to ensure that the TRePYP method can account for both quality degradation issues and changes in the test-rework workload.

Warpage Measurement of Board Assemblies Using Projection MoirÉ System With Improved Automatic Image Segmentation Algorithm

Out-of-plane displacement (warpage) has been a major reliability concern for board-level electronic packaging. Printed wiring board (PWB) and component warpage results from coefficient of thermal expansion (CTE) mismatch among the materials that make up the printed wiring board assembly (PWBA). Warpage occurring during surface-mount reflow process and normal operations may lead to serious reliability problems. PWB/PWBA warpage can be measured by many different optical techniques, among which moire methods have emerged as real-time, noncontact, full-field, and superior techniques with high resolutions. In this paper, a warpage measurement system based on the projection moire technique and improved automatic image segmentation algorithm is presented. In order to use the projection moire system to accurately and separately determine the warpage of a PWB and assembled chip packages in a PWBA, a novel automatic image segmentation algorithm was developed. The algorithm uses mask image models to detect and segment assembled packages from the PWB, and defines their warpage, respectively. This approach resulted in higher resolution and processing rate compared to the original algorithm based on snakes. The warpage of the PWB and chip packages in a PWBA can be successfully determined individually irrespective of the package locations and orientations. Real-time continuous and composite Hermite surface models were generated to evaluate the PWB warpage values underneath packages. The improved segmentation algorithm was integrated with the projection moire system so that the system is able to accurately evaluate the warpage of the PWB and chip packages in a PWBA, respectively.

Simultaneous Measurement of PWB and Chip Package Warpage Using Automatic Image Segmentation

The shadow moire and projection moire techniques are widely used methods for measuring printed wiring board (PWB) and PWB assembly (PWBA) warpage. Both methods have high resolution, high accuracy and are suitable for use in an online environment. When measuring the warpage of a bare PWB, maximum warpage across the PWB is calculated by subtracting the minimum out-of-plane displacement on the PWB from the maximum out-of-plane displacement on the PWB. However, when the PWB is populated with electronic components (chip packages); the difference between the maximum and minimum out-of-plane displacements on the PWBA is not the warpage of the PWB or the warpage of the chip packages. In order to use warpage measurement methods such as the shadow and projection moire techniques to accurately and separately determine the warpage of a PWB and chip packages in a PWBA, an automated chip package segmentation algorithm is developed and will be presented in this paper. The automated algorithm is based on active contour models (snakes) and can be used to detect chip package locations on an out-of-plane displacement image of a PWBA. This paper will discuss the characteristics of the automated algorithm, which is applicable to all warpage measurement methods, not just the out-of-plane moire methods. Warpage case studies of PWBs populated with plastic ball grid array chip packages measured using the projection moire technique will also be presented and will show that the developed algorithm along with a warpage measurement method is a powerful tool for measuring the warpage of populated PWBs.

Fatigue Assessment of Solder Bumps on Board Assemblies Affected by PWB Warpage

Out-of-plane displacement (warpage) has been a major reliability concern for board-level electronic packaging. Printed wiring board (PWB) and component warpage results from CTE mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount assembly processes and normal operations may lead to severe solder bump failures. In this research, the effect of PWB warpage on the low cycle fatigue of the solder bumps in plastic ball grid array (PBGA) packages was studied. Finite element modeling (FEM) was used for the strain-based life prediction of solder bumps on board assemblies. In this paper, 3-D models of PWBAs with varying board warpage were used to estimate the solder bump fatigue life for different types of PBGAs mounted on PWBs. In order to improve the accuracy of FE results, the projection moiré method was used to measure the initial warpage of PWBs, and this warpage was used as a geometric input to the FEM. The PWBAs with known PWB warpage were modeled to determine the influence of various levels of initial PWB warpage on the low cycle fatigue failure of solder bumps. The effect of different types of PBGAs with varying locations on solder bump fatigue was studied. Both Sn-Pb and lead-free solder materials were used in this study. The FE models were validated with experimental results obtained using the projection moiré technique. The FE results showed that the initial PWB warpage has significant a effect on the fatigue reliability of solder bumps in PBGA packages.

Parametric study of warpage in printed wiring board assemblies

Out-of-plane displacement (warpage) causes mis-registration, delamination, possibly solder joint opening(s), and other printed wiring board assembly (PWBA) failures during surface-mount assembly processes and life-span operations. Many material, geometry, and process related parameters contribute to the warpage of a PWBA. The objective of this paper is to investigate these parametric effects on PWBA warpage. Based on the parametric study, the identified material, geometry, and process parameters can then be optimized to achieve the most reliable product. In this paper, a PWBA test vehicle consisting of a four-layer PWB and a surface-mount ball grid array package is studied. Its warpage during infrared reflow is measured by the shadow moire/spl acute/ method to validate finite-element results. The validated modeling results are used for parametric study. In the parametric study, Taguchi and full-factorial design of experiments (DOE) are adopted to systematically vary parameters that are of interest. After running experiments based on DOE, analysis of variance is employed to identify the influential parameters. Thereafter, the warpage data is regressed with respect to the identified influential parameters. According to the regression model, the influential parameters can be optimized within practical range to achieve the least warped design.

Methodology for an Integrated (Electrical/Mechanical) Design of PWBA

This paper describes a general methodology of how electrical circuit design data are mapped into an intermediate analyzable representation that supports the information requirement of several thermomechanical analyses, including product optimization/idealization. This paper describes other issues encountered, such as how to integrate product data that spans more than one tool, how to modify and add analysis data necessary during analysis, and how to use data stored in the analysis module from different programing environments. The advantage this process offers is also described by considering a PWBA (Printed Wiring Board Assembly) design, such as layout and layup in an electrical design system.

Optimal versus heuristic scheduling of surface mount technology lines

This paper presents and compares an exact and a heuristic approach for scheduling of printed wiring board assembly in surface mount technology (SMT) lines. A typical SMT line consists of several assembly stations in series and/or in parallel, separated by finite intermediate buffers. The objective of the scheduling problem is to determine the detailed sequencing and timing of all assembly tasks for each individual board, so as to maximize the line's productivity, which is defined in terms of makespan for a mix of board types. The limited intermediate buffers between stations result in a scheduling problem with machine blocking, where a completed board may remain on a machine and block it until a downstream machine becomes available. In addition, limited machine availability due to scheduled downtimes is considered. The exact approach is based on a mixed integer programming formulation that can be used for optimization of assembly schedules by using commercially available software for integer programming, whereas the heuristic approach is designed as a combination of tabu search and a set of dispatching rules. Numerical examples modelled after real-world SMT lines and some computational results are provided to illustrate and compare the two approaches.

An exact approach for batch scheduling in flexible flow lines with limited intermediate buffers

The paper presents a mixed integer programming approach for makespan minimization in flexible flow lines. The line consists of several processing stages in series, separated by finite intermediate buffers, where each stage has one or more parallel identical machines. The problem objective is to determine a minimum length schedule for a mix of part types, where identical parts are scheduled consecutively. The limited intermediate buffers between the stages result in a scheduling problem with machine blocking, where a completed part may remain on a machine and block it until a downstream machine becomes available. Numerical examples modeled after real-world surface mount technology lines for printed wiring board assembly are provided and some computational results are reported to illustrate the approach.

SCHEDULING OF PRINTED WIRING BOARD ASSEMBLY IN SURFACE MOUNT TECHNOLOGY LINES

The paper presents a new mathematical programming approach for scheduling of printed wiring board assembly in SMT (Surface Mount Technology) lines. Various configurations of SMT lines encountered in the electronics industry are described and compared. An SMT line consists of several processing stages in series, separated by finite intermediate buffers, where each stage has one or more identical parallel machines. A board which has completed processing on a machine may remain there and block the machine until a downstream machine becomes available for processing. The objective is to determine an assembly schedule for a mix of board types, so as to complete the boards in minimum time. New mixed integer programming formulations are presented for blocking scheduling of various configurations of SMT lines that are found in the electronics industry. The proposed models can be used for optimization of assembly schedules by using commercially available software for discrete programming. Numerical examples are provided to illustrate the proposed approach. The influence of process time variability and machine breakdowns on an SMT line's performance is discussed.

Mixed integer programming for scheduling surface mount technology lines

This paper presents new mixed integer programming formulations for blocking scheduling of SMT (Surface Mount Technology) lines for printed wiring board assembly. The SMT line consists of several processing stages in series, separated by finite intermediate buffers, where each stage has one or more identical parallel machines. A board that has completed processing on a machine may remain there and block the machine until a downstream machine becomes available for processing. The objective is to determine an assembly schedule for a mix of board types so as to complete the boards in a minimum time. Scheduling with continuous or with limited machine availability is considered. Numerical examples and some computational results are presented to illustrate applications of the models proposed.

A model for line capacity design for PWB assembly systems

In a multi-product, flexible manufacturing environment, line capacity of printed wiring board (PWB) assembly systems may need to be designed at the beginning of each aggregate planning period because of demand fluctuation over multiple periods. A model of line capacity design problem and production planning at the aggregate level is developed, in which production and subcontracting are assumed to be two options for a firm to meet market demand. The model presented is a large-scale integer programming problem, it cannot be solved by using standard- or mixed-integer programming codes. Under the assumption that each machine line is dedicated to produce one product family, the model can be decomposed as a relatively small subproblem, and each subproblem has good properties by which the subproblems can be further simplified and decomposed over multiple planning periods. As the result, the original large-scale two-stage integer programming problem can be approximately solved by solving a series of small-scale mixed-integer programming, which can be implemented on a workstation or a PC. Computational studies show that the solution method is developed which gives near-optimal solutions with much less computational effort.

Aggregate line capacity design for PWB assembly systems

In a multi-product, flexible manufacturing environment, line capacity of printed wiring board (PWB) assembly systems may need to be adjusted at the beginning of each aggregate planning period because of demand fluctuation over multiple periods. A model of production planning and equipment changeover scheduling at the aggregate level is developed. In the described model, three kinds of equipment changeover methods, i.e. adding machine, removing machine and transferring machine, are involved. Because the model is a large-scale integer programming problem, it cannot be solved directly. A solution approach is developed, which first solves a recursive linear programming problem to obtain a rough set of machines to be added and a rough set of machines to be removed for each machine line in each period, then applies a branch and bound heuristic to the rough sets to obtain near-optimal solutions to the equipment changeover scheduling problem. Computational studies show the financial benefit both on capital cost and equipment changeover costs.

Warpage studies of HDI test vehicles during various thermal profilings

New techniques and technologies involved in the miniaturization of printed wiring board (PWB) fabrication are rapidly emerging. The quality, performance, and reliability of surface mount assemblies built on these next-generation boards will depend on many factors, including thermally induced warpage. Therefore, quantitative warpage measurement is critical in new PWB assembly design evaluation, and determining overall thermal performance characteristics. Using an automated infrared reflow oven simulation system, the warpage of six bare high density interconnect (HDI) samples is measured under two different heating profiles. Out-of-plane surface displacement is measured with a noncontact shadow Moire technique and resolution enhancement method called phase-stepping. The two types of samples evaluated were built for the purpose of warpage study, where physical data could be used to validate finite element analysis (FEA) results. The warpage results obtained with the two thermal profiles will be presented.

Process planning for manual PWB assembly

This paper discusses a Computer Aided Process Planning (CAPP) system which was developed for use in a microelectronics Printed Wiring Board (PWB) assembly facility which specializes in contract manufacturing. This CAPP system focuses on the manual PWB assembly process. It is implemented on a central processor within a star topology Local Area Network (LAN) system. The CAPP system is described, and its inputs and outputs are delineated.