Pre-amorphization Implantation Research Articles

Co-implantation with conventional spike anneal solutions for 45nm n-type metal-oxide-semiconductor ultra-shallow junction formation

Co-implantation schemes for sub-65nm n-type extension formation have been explored. These included phosphorous (P) and arsenic (As) implants into crystalline Si as well as combinations using higher energy silicon pre-amorphization implant (PAI) steps together with low energy carbon (C) implantation. Dopant energies were varied between 500eV and 1keV, with C dose of1×1015cm−2 and P and As doses of 7×1014cm−2. The anneal step was a fast ramp-up and ramp-down spike at 1050°C. Comparisons with dopant-only implants or with PAI and dopant only showed these two schemes to give deeper, more gradual and less well activated junctions than when combined with C. The best result was obtained using a 25keV Si PAI, 6keV C and 1keV P, resulting in a junction depth of 20.5nm at 1×1019cm−3, and Rs=318Ω∕◻ and a 3nm∕dec trailing slope.

Modeling and Simulation of the Influence of SOI Structure on Damage Evolution and Ultra-shallow Junction Formed by Ge Preamorphization Implants and Solid Phase Epitaxial Regrowth

AbstractPreamorphization implant (PAI) prior to dopant implantation, followed by solid phase epitaxial regrowth (SPER) is of great interest due to its ability to form highly-activated ultra-shallow junctions. Coupled with growing interest in the use of silicon-on-insulator (SOI) wafers, modeling and simulating the influence of SOI structure on damage evolution and ultra-shallow junction formation is required. In this work, we use a kinetic Monte Carlo (kMC) simulator to model the different mechanisms involved in the process of ultra-shallow junction formation, including amorphization, recrystallization, defect interaction and evolution, as well as dopant-defect interaction in both bulk silicon and SOI. Simulation results of dopant concentration profiles and dopant activation are in good agreement with experimental data and can provide important insight for optimizing the process in bulk silicon and SOI.

Preamorphization implantation-assisted boron activation in bulk germanium and germanium-on-insulator

The effect of preamorphization implantation (PAI) on boron activation in germanium was studied. It was found that following PAI, significant dynamic annealing occurred during boron implantation in germanium. For small PAI energy which leads to a thin amorphous layer, recrystallization is completed via dynamic annealing during the boron implantation. As a result, a high-temperature postimplant anneal is required to activate the remaining interstitial boron and to annihilate implantation defects. For high PAI energy, while the thick amorphous layer did not recrystallize during the dynamic annealing, it requires a high-temperature anneal in order to completely recrystallize by solid phase epitaxial regrowth (SPER). The optimized PAI energy needs to be tailored such that the surface amorphous layer not only survives dynamic annealing during boron implantation, but also completes the SPER within the designed thermal budget. Full activation of boron can then be achieved without being limited by its solid solubility in germanium. An electrically active boron concentration as high as 4.7×1020∕cm3 was obtained after 400°C rapid thermal annealing. PAI causes a similar effect in GeOI substrates.

Optimization of pre-amorphization and dopant implant conditions for advanced annealing

As CMOS device dimensions shrink toward the 45nm technology node, the junction depth of the source/drain extensions must decrease to 7–12nm in order to minimize short channel effects. Simultaneously, the desire for high transistor drive currents and fast device performance leads to the requirement of a maximum PMOS extension sheet resistance of 830Ω/□. In order to meet the junction depth requirement, advanced annealing techniques with maximum temperature dwell times of about 1ms are being developed and assessed, since they enable dopant activation with minimal diffusion from the as-implanted dopant profile. Nevertheless, achieving low sheet resistances with junctions formed by these advanced anneals is a challenge. Pre-amorphization with Ge+ ions is commonly used to reduce the as-implanted junction depth by minimizing channeling, but the pre-amorphization implant conditions influence the junction sheet resistance along with the dopant implant conditions. This paper will discuss an optimization study of pre-amorphization and dopant implant conditions with advanced annealing for PMOS source/drain extension formation. The energy and dose of Ge+ pre-amorphization implants and B+ dopant implants were varied to find the minimum sheet resistance and junction depth. The optimal implant conditions for advanced anneal are found to be different from those previously reported for spike anneal. Two types of dopant activation mechanisms will be discussed to explain the different sets of optimum conditions. In addition, the boron diffusion appears to be controlled by the Ge peak position, which can be used to improve profile abruptness. These mechanisms together appear to provide the knobs that enable formation of p+–n junctions satisfying the ITRS 45nm requirements.

Roughness of amorphous/crystalline interface in pre-amorphization implantation: Molecular dynamic simulation and modeling

Pre-amorphization implantation has been applied as a shallow junction technology. Roughness at amorphous/crystalline (a/c) interface should be controlled to improve junction characteristics. To understand and model a/c interface roughness, molecular dynamic method is applied in simulating pre-amorphization implantation. A method to reproduce roughness at a/c interface by molecular dynamic simulation is presented. A model of interface roughness is presented. Si and Ge implantation from 2–20 keV at a dose of 1 × 10 15 cm −2 is simulated. The depth of a/c interface is reproduced. Experimental results of a/c interface roughness are successfully simulated. The interface roughness is well reproduced and interpreted by the model presented.

Ultrashallow Junction Formation by Self-Limiting LTP and Its Application to Sub-65-nm Node MOSFETs

We have developed a novel laser thermal process that dramatically enhances laser exposure windows by controlling the heating process in a self-limiting way. Key technology is realized by introducing a new process combination of preamorphization implantation and a heat absorber with a phase switch layer, and by optimizing them. The V/sub th/ rolloffs of MOSFETs formed by this method were remarkably improved compared to those by rapid thermal annealing when offset-spacer and halo-implantation processes were not applied. Its effectiveness was also verified in 50-nm gate complementary metal-oxide semiconductor devices for the first time by confirming that the drain current increased with laser fluence beyond the conventional exposure limit.

Effects of PAI on interface properties between HfSiO gate dielectric and silicon substrate

The effects of preamorphization implantation (PAI) on the interface properties between hafnium-silicate (HfSiO) gate dielectrics and silicon substrates were examined. In the case of an NH/sub 3/ nitrided interface, it was found that the PAI can improve the interface trap density (D/sub IT/) compared with the no PAI case. However, for the PAI samples, it was also found that samples with sacrificial screening oxide (Sac Ox) had worse interface properties compared with the samples without Sac Ox. It is attributed to the recoiled oxygen from Sac Ox during PAI.

Drive Current Enhancement in Sub-50 nm CMOS by Reduction of SDE Resistance with Laser Thermal Process

In this paper, we report on the ultrashallow junction profiles and good characteristics of sub-50 nm bulk complementary metal oxide semiconductor (CMOS) devices with n+/p+ source-drain extensions (SDEs) formed by laser thermal processing (LTP). By combining LTP with preamorphization and strong-dosage dopant-ion implantation, CMOS drive current can be improved without incurring a cost in terms of short-channel deterioration. The SDE-junction depth, SDE overlap length, and sheet resistance were controlled by the energy of preamorphization implantation, and the first two of these parameters were independent of dopant dosage. This allowed us to design strongly activated and abrupt box-like dopant profiles. With this technique, we obtain improvements in drive current of 13 and 8%, respectively, for p- and n-metal oxide semiconductor field effect transistors at and without inducing any short-channel deterioration. © 2004 The Electrochemical Society. All rights reserved.

Abnormal Oxidation of Nickel Silicide on N-Type Substrate and Effect of Preamorphization Implantation

In this study, the abnormal oxidation of nickel silicide on an n-type substrate and the suppression of the abnormal oxidation by N2 preamorphization implantation (PAI) have been investigated. Although there is little difference in the sheet resistance regardless of dopants just after the silicidation, a strong dependence was observed after high-temperature postsilicidation annealing. Only the As-doped source/drain was oxidized during the postsilicidation annealing, and silicide properties were severely degraded. To prevent the unintended oxidation of the As-doped source/drain, N2 or Ge PAI was implemented and the thermal stability was greatly improved by N2 PAI with a Ti capping layer.

Formation and control of box-shaped ultra-shallow junction using laser annealing and pre-amorphization implantation

A box-shaped doping profile is successfully formed by combining laser annealing (LA) process with pre-amorphization implantation (PAI) technique. The junction depths of box-shaped profiles are precisely controlled by changing PAI energy which in turn changes the melting thickness of silicon layer regardless of arsenic and boron dopant species. The material properties which are related to ultra-shallow junction for sub-100 nm CMOS device application, such as transient enhanced diffusion (TED) and end-of-range defect density are investigated by secondary ion mass spectrometry and transmission electron microscopy. TED phenomena of furnace annealed, rapid thermal annealed (RTA), and LA samples are also compared. Impurity doping profiles annealed by laser do not show significant TED even after taking additional specific RTA step. Sheet resistance characteristics with various implantation conditions and annealing conditions are examined. Large process window margin is achieved by the proposed PAI combined with subsequent multi-shot LA process.

B diffusion in Si with pre-amorphization of different species

Boron diffusion in Si in shallow pre-amorphization implants (SPAI) of different species, including F, Ge, GeF2, BF2, and their combination was studied. Results show that different species have different impact on B diffusion. In addition to the chemical effect, the interaction of SPAI species with B, leading to immobile B clustering, is another important cause for B diffusion reduction. Fluorine is more effective than Ge in the B diffusion reduction. Adding more F in the amorphous region results in more B diffusion reduction. Aside from the effect on the B diffusion, fluorine itself manifests a large amount of out-diffusion for the shallow F implant case and as F is implanted deeper, a bell-shaped F profile exists around the end-of-range damage. The out-diffusion of F is further enhanced by the implanted damage.

Dopant Activation in bulk germanium and Germanium-on-Insulator

ABSTRACTHigh levels of electrical activation of both p- and n-type dopants are realized by pre-amorphization implantation (PAI) in bulk germanium wafers and germanium-on-insulator (GOI) substrates. In bulk germanium, p-type dopant yields an electrical activated concentration of 1.5×1020 /cm3 after a 400°C rapid thermal annealing (RTA), which is one order higher than obtained for samples without PAI. N-type dopants also show comparable improvement as 1×1020 /cm3 after 600°C RTA. Both results are the highest ever being reported and are sufficient for advanced CMOS applications. PAI was also employed in dopant activation for GOI substrates. Carrier concentrations of 6×1020 /cm3 and 5×1019 /cm3 were observed for p- and n-type dopants respectively after identical RTA conditions as for bulk germanium counterparts. Hydrogen incorporated in GOI wafers which were prepared by Smart-Cut™ approach may be responsible for the discrepancy of activated concentrations between bulk germanium and GOI. Nevertheless, PAI shows the promise of dopant activation in germanium and can be readily adopted in current CMOS processes.

Modeling B clustering in Si and SiGe

ABSTRACTOur experiments show boron-interstitial cluster dissolution is reduced during oxidation, a behavior not predicted by the current models. Both our experiments and others on the time dependence indicate the reactivation is coming from more than one cluster. Since oxidation induced interstitial injection reduces reactivation, one of the significant clusters has to release an interstitial release during dissolution. Recent ab-initio calculations provide a qualitatively different B clustering model, with two significant cluster species. Based on these energetics, we have developed a new physically based model that for the first time accounts for the experimentally observed cluster dissolution time and ambient dependence.Anomalous B diffusion behavior is also observed in an investigation of Ge influence on B diffusion. Silicon wafers were subjected to a Si preamorphization implant (PAI), followed by Ge and B implants contained within the existing amorphous layer. The control sample received only Si PAI and B implant. Upon annealing, the peak of the B profile shifts towards the surface and increases in magnitude, exhibiting uphill diffusion. The control samples subjected to the same thermal processing exhibit TED, but no uphill diffusion behavior. This is consistent with the model of B diffusion in Si1−xGex, accounting for trapping of B at Ge sites through formation of GeB complex.

X-ray and secondary ion mass spectrometry investigation of activation behavior of self-preamorphized silicon substrate

The junctions for p-type source/drain and extensions for sub-100 nm technology nodes can be formed by using low energy beamline implantation, plasma doping, or elevated source/drain approaches in conjunction with various thermal processing methods. An important objective for sub-100 nm junction engineering is incorporation and activation of desired level of dopant in the junction region. In this article, the interaction between Si preamorphization implantation and boron implantation has been investigated by using secondary ion mass spectrometry (SIMS), triple crystal x-ray diffraction (XRD), and four point probe measurements. The dopant profile abruptness is found to be a function of boron energy and the Si+ ion dose and energy. Results demonstrate that an increase in Si energy by 10 keV yields ∼100 Å shallower and more abrupt boron profiles. Crystallinity of the implanted layer after thermal treatment has been characterized by the triple crystal XRD technique. The XRD rocking curve data correlated well with Rs and the SIMS measurements indicating lattice damage recovery and dopant activation.

Process Optimization for Multiple-Pulses Laser Annealing for Boron Implanted Silicon with Germanium Pre-amorphization

AbstractOne of the major advantages of multiple-pulses Laser Thermal Annealing (LTA) with moderate energy fluence is that good dopant activation can be achieved without further increases in junction depth by successive pulses. It is demonstrated that when the laser fluence is adjusted to a value that can melt the preamorphization implantation (PAI) layer but not the underlying silicon substrate, PAI layer depths control the junction depths. Hence, it is desirable to operate LTA in this regime since this allows for a tighter process control as opposed to when the junction depth is controlled solely by the laser fluence. High Resolution Transmission Electron Microscopy (HR-TEM) micrographs show that the degree of damage repair depends on the amorphous layer thickness as well as the number of pulses. Our study allows for the evaluation of the maximum allowable PAI depth for a given number of pulses in order to fully remove the damage caused by the PAI.

Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS

Source/drain (S/D) engineering for ideal box-shaped junction formation using laser annealing (LA) combined with pre-amorphization implantation (PAI) is proposed and implemented in device integration for sub-100-nm CMOS on an SOI substrate. Modeling analysis for the resistance component associated with junction profile abruptness demonstrates that a noticeable reduction in parasitic series resistance with technology generation can be achieved through junction profile slope engineering. From the experimental results of LA, it is found that PAI not only controls the ultrashallow junction depth precisely, but also reduces the laser energy fluence required for impurity activation. In addition, laser annealing energy can be further reduced by use of SOI substrates in the device integration, indicating the implementation feasibility of LA to CMOS integration with an enlarged process window margin. The proposed S/D engineering is verified by the sheet resistance of junctions and the fabricated device current characteristics exhibiting substantially improved short-channel performance with higher current capability due to the box-shaped junction profile as compared with conventional rapid thermally-annealed (RTA) devices.

Comparative study of double ion implant Ti–salicide and pre-amorphization implant Co–salicide for ultra-large-scale integration applications

We have investigated the interesting double ion implant (DII) Ti–salicide and pre-amorphization implant (PAI) Co–salicide techniques for ultra-large-scale integration (ULSI) applications. The DII technique is combined with germanium (or arsenic) PAI and Si ion-mixing processes. The sheet resistances both of n+ and p+ polysilicons are decreased when the DII Ti–salicide and PAI Co–salicide techniques are used. Moreover, the incomplete phase transformation of Ti–salicide is not observed in 0.2 μm wide polysilicon devices with the Ge DII process. Furthermore, the n+/p-well junction leakage current is reduced when the Si ion-mixing process is used. Experimentally, based on the studied DII Ti–salicide and PAI Co–salicide techniques, high-performance 0.2 μm CMOS devices have been successfully fabricated.

Ultrashallow Junction Formation for Sub-100 nm Complementary Metal-Oxide-Semiconductor Field-Effect Transistor by Controlling Transient Enhanced Diffusion

The annealing process of implantation damage that induces transient enhanced diffusion during a subsequent thermal process such as low-pressure chemical vapor deposition (LPCVD) is optimized from the viewpoint of the process integration of an 80 nm physical gate length complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) device. For nMOSFETs, a temperature as high as 960°C is necessary to prevent transient enhanced diffusion. In contrast, for pMOSFETs, higher temperature annealing promotes thermal diffusion instead of preventing enhanced diffusion. It is found that a separate annealing process sequence is required. In utilizing preamorphization implantation prior to boron implantation, however, higher temperature annealing is effective for forming an ultrashallow junction. Consequently, the annealing processes can be performed simultaneously.

Shallow Junctions for Sub-100 Nm Cmos Technology

ABSTRACTThis paper studies the use of ion implantation and rapid thermal annealing for the fabrication of shallow junctions in sub-100 nm CMOS technology. Spike annealing recipes were optimized on the basis of delta-doping diffusion experiments and shallow junction characteristics. In addition, using GeF2 pre-amorphization implants in combination with low-energy BF2 and spike annealing, p-type junctions depths of 30 nm were obtained with sheet resistances as low as 390 Ω/sq. The combined finetuning of implantation and annealing conditions is expected to enable junction scaling into the 70-nm CMOS technology node.

High sensitivity measurement of implanted As in the presence of Ge in GexSi1−x/Si layered alloys using trace element accelerator mass spectrometry

Various devices can be realized on strained GeSi/Si substrates by doping the substrate with different impurities such as As. As is an n-type dopant in both Ge and Si. As cross contamination can also arise during germanium preamorphization implantation due to inadequate mass resolution in the implanter. Thus, it is important to be able to accurately measure low-level As concentrations in the presence of Ge. Secondary ion mass spectrometry (SIMS) is the standard technique for these types of measurements but is constrained by mass interferences from molecular ions (74GeH, 29Si30Si16O). The trace element accelerator mass accelerator technique allows the breakup of interfering molecules. As is measured in a GeSi matrix with sensitivity significantly better than SIMS.