Optimization of pre-amorphization and dopant implant conditions for advanced annealing

Abstract

As CMOS device dimensions shrink toward the 45nm technology node, the junction depth of the source/drain extensions must decrease to 7–12nm in order to minimize short channel effects. Simultaneously, the desire for high transistor drive currents and fast device performance leads to the requirement of a maximum PMOS extension sheet resistance of 830Ω/□. In order to meet the junction depth requirement, advanced annealing techniques with maximum temperature dwell times of about 1ms are being developed and assessed, since they enable dopant activation with minimal diffusion from the as-implanted dopant profile. Nevertheless, achieving low sheet resistances with junctions formed by these advanced anneals is a challenge. Pre-amorphization with Ge+ ions is commonly used to reduce the as-implanted junction depth by minimizing channeling, but the pre-amorphization implant conditions influence the junction sheet resistance along with the dopant implant conditions. This paper will discuss an optimization study of pre-amorphization and dopant implant conditions with advanced annealing for PMOS source/drain extension formation. The energy and dose of Ge+ pre-amorphization implants and B+ dopant implants were varied to find the minimum sheet resistance and junction depth. The optimal implant conditions for advanced anneal are found to be different from those previously reported for spike anneal. Two types of dopant activation mechanisms will be discussed to explain the different sets of optimum conditions. In addition, the boron diffusion appears to be controlled by the Ge peak position, which can be used to improve profile abruptness. These mechanisms together appear to provide the knobs that enable formation of p+–n junctions satisfying the ITRS 45nm requirements.