Power Device Packaging Research Articles

Thermally stable Cu3Sn/Cu composite joint for high-temperature power device

This paper describes a novel transient liquid phase sinter (TLPS) bonding that utilizes Sn-coated micro-sized Cu particles for high-temperature power device packaging. When used as die attach materials for Cu–Cu bonding, a thermally stable joint comprising a Cu3Sn intermetallic compounds (IMCs) with a dispersion of ductile Cu particles was obtained after bonding at 300°C for 30s, and a shear strength equivalent to that of conventional Pb–5Sn solder could be achieved. After isothermal aging at 300°C for 200h, the shear strength and microstructure of the bonding joints were almost unchanged.

Nondestructive Measurement of Discontinuous Deformation at Internal Interfaces of Power Device Package

Nondestructive Measurement of Discontinuous Deformation at Internal Interfaces of Power Device Package

Silver nanoporous sheet for solid-state die attach in power device packaging

A novel die attach process that utilizes an Ag nanoporous sheet has been investigated for power device packaging. This Ag nanoporous sheet, which has a ligament size of about 110 nm, was fabricated through the dealloying of Al–Ag precursor in hydrochloric acid. When used as a die attach layer, no large voids or gaps were observed in the interfacial area, and a shear strength equivalent to conventional Pb–5Sn solder could be achieved without the need for any organic substances.

파워디바이스 패키징의 열제어 기술과 연구 동향

Technology for high power devices has made impressive progress in increasing the current density of power semiconductor, system module, and design optimization, which realize high power systems with heterogeneous functional integration. Depending on the performance development of high power semiconductor, packaging technology of high power device is urgently required for efficiency improvement of the device. Power device packaging must provide superior thermal management due to high operating temperature of power modules. Here we, therefore, review critical challenges of typical power electronics packaging today including core assembly processes, component materials, and reliability evaluation regulations.

Fluxless bonding of Si chips to aluminum boards using electroplated Sn solder

The high thermal conductivity and light weight properties of aluminum (Al) make it a promising material in high power device packaging and automotive electronics. A primary challenge is its high coefficient of thermal expansion (CTE) of 23 ppm/°C. In this research, we investigated the possibility of surmounting this challenge by bonding large Si chips to Al substrates using fluxless tin (Sn) solder. The Si–Al pair probably has the largest CTE mismatch among all bonded structures in electronic packaging. In experiments, 0.1 μm Cr layer and 0.2 μm Cu layer were deposited on Al substrates, followed by an electroplated 25 μm copper (Cu) layer. The Sn solder layer was then electroplated over the Cu, followed immediately by thin (0.1 μm) silver (Ag) layer. The joint thickness was controlled either by bonding pressure or by incorporating Cu spacers. Microstructure and composition of the joints were studied with scanning electron microscopy and energy dispersive X-ray spectroscopy. Despite the large CTE mismatch, the bonded structures did not break. The minimum fracture force measured among six samples by shear test is higher than three times of what specified in MIL-STD-883H, method 2019.8. This preliminary result corroborates potential adaption of Al substrates and boards in electronic packaging where lightweight is essential.

Evaluation of Thermal Cycling Reliability of Sintered Nanosilver Versus Soldered Joints by Curvature Measurement

Low-temperature silver sintering technology is emerging as a lead-free die-attach solution to significantly improve the heat dissipation and reliability packaging of power devices and modules die attached by solder alloys. With the recent introduction of nanosilver materials, which dramatically simplify the bonding process by lowering the required pressure down to a few megapascals, the silver sintering die-attach solution is poised for wide use in the manufacture of electronic products. In this paper, the thermomechanical reliability of sintered-silver joints was studied in comparison with soldered joints of two lead-free solders, SN100C and SAC305. Die-attach samples were fabricated by bonding 10 mm × 10 mm silicon mechanical chips to silver-metalized copper blocks and direct-bond copper (DBC) substrates according to the respective heating profiles of a nanosilver paste and the two solders. The die-attach samples were thermally cycled between -40 °C and +125 °C. The bonding reliability was evaluated by measuring the bending curvatures of the cycled samples and examining the cross sections of the samples under an electron microscope. Bending of the bonded structures, which is the result of mismatched coefficients of thermal expansion between silicon and copper or DBC, offered a nondestructive method for monitoring the integrity of the bond line. The bending curvatures of all of the die-attach samples decreased rapidly after they were thermally cycled. Most of the drop in curvature can be attributed to stress relaxation in the bonding materials without bond-line cracking. However, in the samples on copper blocks, after 800 cycles, the curvatures of the soldered samples decreased to near 0 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> , but those of the silver-sintered samples still had about 30% of the original curvatures. Scanning electron microscopy images showed that the joints of the soldered samples with near 0 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> curvature had been cracked almost all the way through, but the joints of the sintered samples were still intact. These results demonstrate that the sintered-silver joints are more reliable than the soldered joints.

Pressure Dependence of Thermal Contact Resistance between Copper Heat Sink and Copper DBC Surfaces in SiC Power Device Packages

Thermal contact resistances have been measured in an experiment emulating heat transfer from a SiC die to a cooled heat sink through a heat spreader and a DBC structure. The major surface-dependent parameters are the surface roughness, surface hardness, and planarity. The measured thermal contact resistances are in agreement with theoretical values. When investigating DBC copper surfaces a second interface between the bonded Cu to AlN has to be taken into account.

Finite element analysis of the effect of silver content for Sn–Ag–Cu alloy compositions on thermal cycling reliability of solder die attach

Thermal performance of a chip-scale packaged power device can be improved by attaching a heat spreader to the backside of the heat generating silicon die via solder thermal interface materials [STIMs]/solder die-attach. Driven by government legislation, electronics industry has advanced to lead (Pb)-free solders due to environmental and health concerns emanating from the use of Pb-based solders. Though solder compositions in the form of Sn–Ag–Cu (SAC) ternary system have been widely accepted and preferred by the electronic industry as replacements for the traditional Pb-based solder alloys, debate continues over the optimal silver content in the Sn–Ag–Cu (SAC) solder alloys. Apparently, the effect of silver (Ag) content on thermo-mechanical reliability of SAC alloy compositions as small area solder joints (flip chip solder bump or ball grid array (BGA)) has been extensively studied but not enough information exist on the effect of Ag percentage in SAC solder alloys when employed as large area solder joint (die-attach application). In this study, non-linear finite element method (FEM) is used for a comparative analysis of the effect of Ag content on the thermal fatigue performance of Sn–3Ag–0.5Cu (SAC305) and Sn–4Ag–0.5Cu (SAC405) when used in die-attach applications under three different thermal cyclic loading cases. The results show that Von-Mises stresses and strain energy in each of the two different SAC solder joints were strong function of the thermal cycle profiles, increasing in the order −55–80°C<−55–125°C<−65–150°C. In addition, this study suggests that the range of stress was relatively greater for the SAC alloy with higher Ag content (SAC405) while the lower Ag content SAC solder (SAC305) experiences a comparatively larger accumulated plastic work under the same thermal cycling condition. Further failure analysis via visual inspection reveals that for all cases of thermal cyclic loading employed in this study, maximum values of strain energy were all located in the corner regions (critical regions) of the solder joints at the side next to the silicon die independent of the Ag content of the solder joints. This paper also highlights the concerns as regards the implementation of conventional thermal fatigue models for accurate life time prediction of large area solder joint.

Shrinkage and Sintering Behavior of a Low-Temperature Sinterable Nanosilver Die-Attach Paste

The drying and densification behavior of a nanosilver paste was studied by shrinkage and weight-loss measurements to provide fundamental understanding on the sintering behavior of the nanomaterial for packaging power devices and modules. The measured shrinkage behavior was found to be in good agreement with the weight-loss behavior of the paste as measured by thermogravitational analysis, and the comparison offered direct evidence of ~10% shrinkage contributed by late-stage densification of silver nanoparticles (NPs). It was found that sintered silver joints could be achieved without cracks or delamination under a ramp-soak temperature profile for bonding small-area chips, e.g., 3 mm × 3 mm or smaller. However, for bonding large-area chips, e.g., 5 mm × 5 mm or larger, rapid evaporation of the entrapped organic species caused the chips to delaminate, leading to large longitudinal cracks at the joint interface. Finally, examination of the microstructure evolution of the silver die-attach material revealed that binder molecules inhibited necking of the silver NPs and delayed densification during the sintering process of the nanosilver paste.

Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device

Chip scale package (CSP) technology offers promising solutions to package power device due to its relatively good thermal performance among other factors. Solder thermal interface materials (STIMs) are often employed at the die bond layer of a chip-scale packaged power device to enhance heat transfer from the chip to the heat spreader. Nonetheless, the presence of voids in the solder die-attach layer impedes heat flow and could lead to an increase in the peak temperature of the chip. Such voids which form easily in the solder joint during reflow soldering process at manufacturing stage are primarily occasioned by out-gassing phenomenon and defective metallisation. Apparently, the thermal consequences of voids have been extensively studied, but not much information exist on precise effects of different patterns of solder die-attach voids on the thermal performance of chip-level packaged power device. In this study, three-dimensional finite element analysis (FEA) is employed to investigate such effects. Numerical studies were carried out to characterise the thermal impacts of various voids configurations, voids depth and voids location on package thermal resistance and chip junction temperature. The results show that for equivalent voiding percentage, thermal resistance increases more for large coalesced void type in comparison to the small distributed voids configuration. In addition, the study suggests that void extending through the entire thickness of solder layer and voids formed very close to the heat generating area of the chip can significantly increase package thermal resistance and chip junction temperature. The findings of this study indicate that void configurations, void depth and void location are vital parameters in evaluating the thermal effects of voids.

Fast 3D thermal simulation of power module packaging

SUMMARYThis paper presents a thermal model that uses a Fourier series solution to the heat equation to carry out transient 3D thermal simulation of power device packaging. The development and implementation of this physics‐based method is described. The method is demonstrated on a stacked 3D multichip module. The required aspects of 3D heat conduction are captured successfully by the model. Compared with previous thermal models presented in literature, it is fast, accurate and can be easily integrated with an inverter circuit simulator to model realistic converter load cycles. Copyright © 2012 John Wiley &amp; Sons, Ltd.

Effect of Oxygen Partial Pressure on Silver Migration of Low-Temperature Sintered Nanosilver Die-Attach Material

The low-temperature joining technique of silver sintering is being actively pursued in the power electronics industry as a lead-free die-attach solution for packaging power devices and modules. However, one of the concerns of this technique is the migration of silver at a high temperature. Recently, we have reported our findings of the migration of a low-temperature sintered nanosilver in dry air at a temperature over 250°1C. In this paper, we report our results of the effect of oxygen partial pressure on the migration kinetics of the sintered nanosilver at 400°C under an electrical field strength of 50 V/mm. The range of the oxygen partial pressure tested was between <; 0.01 and 0.40 atm. The silver migration kinetics were monitored by measuring the leakage current across a metal-finger pattern, which allowed the determination of the lifetime, or the onset time for significant leakage current developed across the two electrodes. With decreasing oxygen partial pressure, the lifetime increases exponentially. Our results suggest that the concern for silver migration in a high-temperature application of sintered silver die attach can be effectively remedied through packaging to keep oxygen away from the silver joints.

プリント配線板を支える高分子材料 プリント配線板の現状と今後の展望

Personal digital assistants (PDA), such as cellular phones, personal computers and car navigation systems, supporting the ubiquitous society, is expected to be the smart phones which have above mentioned all functions and evolve to ultimate wearable PDAs. High density LSI packaging technologies have been realized the superior performance and function of communication electronics products and printed wiring boards have played very important role to meet these requirements. Here, after brief introduction of the history and the categories, the technologies and the recent trend for the printed wiring boards are introduced, especially focusing on the thermosetting polymer materials. As the future prospect, we pay attention to the automotive electronics field, concretely the power device packaging technologies. High heat resistant and low thermal expansion resins such as polyaromatic epoxy resins, benzoxazine resins and cyanate resins for power semiconductor module are developed. Power semiconductor devices are key devices for carbon dioxide reduction technology. As another approach, the effective use of biomass resources as industrial materials plays an important role. Lignin is a plant biomass and is classified as a polyphenol and investigated a suitable alternative to fossil-fuel-derived phenol resins for use in the thermosetting epoxy resins.

Large-Area Chip Attachment by Sintering Nanosilver Paste: Process Improvement by Nondestructive Characterization

Low-temperature joining with sintered silver is being developed as a lead-free, non-solder, die-attach solution for packaging power devices and modules. While its feasibility has been demonstrated, one major drawback of sintered silver joint is the high applied pressure during sintering to produce the desired bond strength. A high percentage of voids could also remain in the sintered joints. Applying the technique to large-area attachments also means a correspondingly higher applied pressure, and damage to the devices and substrates is possible. This study focused on the use of nanosilver paste as an attachment material that can be sintered at relatively low temperatures and pressures. Because of the difficulty of obtaining the die-shear strength of very large attachments, two non-destructive methods, micro X-ray computed tomography (CT) and curvature measurement using a laser-scanning technique, were used to characterize the bonded structures. Effects of different drying and sintering conditions on the bonding qualities were discussed.

Preparation and characterization of special glasses for sealing and other applications

Glasses find wide applications, among others, in process technologies, vacuum science and technology etc. because of their desired thermo-mechanical properties and chemical durability. In particular, hermetic glass-to-metal (GM) seals are required mainly as electrical feed through for various types of gas based and electron devices, chemical process industries, including for packaging of power devices. The physico-chemical properties of glasses play important role in forming hermetic sealing with metals/alloys. The properties like thermal expansion coefficient, glass transition temperature, micro hardness, chemical durability etc. can be tailored by varying the glass composition by adding multi alkali and alkaline earth metal oxides to the base glass and varying the process parameters. We have prepared different types of glasses for the fabrication of different types of hermetic seals. Some of these are i) Lead silicate (LS) glass having SiO2, Na2O, K2O, BaO and PbO for compression type GM seals with SS304/Inconel and AISI 446 alloy ii) Borosilicate (BS) glass containing SiO2.Na2O.K20. Al2O3.B2O3 for matched type GM seals with Mo/ Kovar alloy and for uptake of synthetic dyes like Rhodamine 6G, Methylene Blue, Uranyl ions in process industries and nuclear industry iii) Sodium alumino phosphate (NAP) glass with P2O5-Na2O-B2O3-BaO- PbO for matched type GM seals with low melting metals (Al,Cu)/alloys like Cu-Be.

Packaging and Interconnection Technologies of Power Devices, Challenges and Future Trends

Packaging and Interconnection Technologies of Power Devices, Challenges and Future Trends

Fluxless bonding of silicon wafers to molybdenum substrates using electroplated tin-rich solder

A novel fluxless bonding process of silicon wafer on molybdenum substrate is successfully developed. Si-to-Mo bonding can be used for packaging power devices, especially when a device consists of an entire wafer. 300 A Cr layer and 1,000 A Au layer are first deposited on Si wafers and Mo substrates. The Cr/Au dual layer is used as underbump metallurgy and seed layer of electroplating. To reduce plastic shear strain on the solder in a bonded pair, thick Sn layer (70 μm) is electroplated over Mo substrates having Cr/Au structure, followed immediately by thin (0.1 μm) Ag layer. This Ag layer acts as the capping layer to prevent inner Sn from oxidation. The bonding process is performed in 50 millitorrs vacuum to inhibit oxidation. The bonding condition is 290 °C for 15 min without the use of any flux. The bonding layer thickness is controlled at 50 μm by small spacers placed between Si wafer and Mo substrate. Microstructure and composition of the joints are studied under scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDX). Scanning acoustic microscopy (SAM) is also used to verify the quality of joints over the entire sample. Without using any flux, high quality and uniform bonding layer is achieved. The composition of the joint is more than 97 at.% Sn. No intermetallic compound layers exist in the joint. This novel fluxless bonding process should be valuable in packaging large high power devices.

シックスシグマによるパワーデバイスパッケージの信頼性設計

シックスシグマによるパワーデバイスパッケージの信頼性設計

Robust Thermal Design for Power Device Package Using Response Surface Method and Monte Carlo Simulation

In the present study, the robust thermal design of a power device package was accomplished using thermal conduction calculation, design of experiment, response surface method and Monte Carlo simulation. Initially, the effects of the design parameters on the solder strain were examined in terms of the thermal expansion difference as a result of unsteady thermal conduction simulation. From the factorial effects of design parameters, the design proposals were screened. Then, robustness of the thermal resistance was evaluated for the three design proposals obtained. The thermal resistances were calculated by solving the steady thermal conduction equation under the design of experiment conditions. The solder thickness, the substrate thickness, and the cooling fin performance were considered as the fluctuation factors, assuming the error associated with manufacturing process. Using a response surface method, the values of thermal resistance were expressed as a function of the design variables. The variances of the thermal resistance were examined based on Monte Carlo simulations. Related to the cooling fin design, the Pareto line showing the trade-off relation between the fin dimension and the fan velocity was obtained. By repeating the Monte Carlo simulations, the Pareto solution was calculated so that the thermal resistances satisfy the criteria in the position of 95 percentile of the thermal resistance variation. Under the same flow velocity conditions, the fin dimensions become about 10% higher compared to the case where the manufacturing error was not taken into account. By carrying out the thermal design following this Pareto line, even if the manufacturing error was taken into consideration, the thermal resistance could satisfy the desired value.

1115 パワーデバイスパッケージの強度・熱協調設計(J08-3 電子情報機器,電子デバイスの強度・信頼性評価と熱制御(3) 基板・部品の特性評価,ジョイントセッション,21世紀地球環境革命の機械工学:人・マイクロナノ・エネルギー・環境)

1115 パワーデバイスパッケージの強度・熱協調設計(J08-3 電子情報機器,電子デバイスの強度・信頼性評価と熱制御(3) 基板・部品の特性評価,ジョイントセッション,21世紀地球環境革命の機械工学:人・マイクロナノ・エネルギー・環境)