Power Device Packaging Research Articles

Power Device Packaging Technologies for Extreme Environments

Silicon carbide is a wide-bandgap semiconductor capable of operation at temperatures in excess of 300degC. However, high-temperature packaging to interface with the other elements of the electrical system is required. Die attach, wire bonding, and passivation materials and techniques have been demonstrated for use at 300degC. Transient liquid phase bonding has been developed with Au:Sn/Au, yielding high die shear strength after 2000 h at 400degC. Large diameter (250 mum) gold and platinum wire bonding was evaluated for top side electrical contact. Au wire was reliable after 2000 h at 300degC with Ti/Ti:W/Au pads over passivation on the SiC. However, Au wire on Ti/Pt/Au and Pt wire on both Ti/Tl:W/Au and Ti/Pt/Au exhibited passivation fracture with aging. Polyimide has been demonstrated for 2000 h at 300degC in air as a high-voltage passivation layer.

Pb-free high temperature solders for power device packaging

Reliabilities of joints for power semiconductor devices using a Bi-based high temperature solder has been studied. The Bi-based solder whose melting point is 270 °C were prepared by mixing of the CuAlMn particles and molten Bi to overcome the brittleness of Bi. Then, joined samples using the solder were fabricated and thermal cycling tests were examined. After almost 2000 test cycles of −40/200 °C test, neither intermetallic compounds nor cracks were observed for CTE (Coefficient of Thermal Expansion) matched sample with Cu interface. On the other hand, certain amount of intermetallic compound such as Bi 3Ni was found for a sample with Ni interface. In addition, higher reliability of this solder than Sn-Cu solder was obtained after −40/250 °C test. Furthermore, an example power module structure using double high temperature solder layers was proposed.

Discussion on the Reliability Issues of Solder-Bump and Direct-Solder Bonded Power Device Packages Having Double-Sided Cooling Capability

Power device packages with solder-bump (SB) and direct-solder (DS) interconnections were fabricated and some of their thermomechanical reliability issues were discussed based on both thermal cycling experiment and finite element analysis (FEA). The SB interconnection shows superior reliability over the DS interconnection in the thermal cycling experiment because the mismatched coefficient of thermal expansion leads to smaller stresses at the SB interconnection under the same temperature changes. On the other hand, FEA results show that the DS package has significantly lower operating temperatures under the same double-sided cooling condition. After considering the operating temperature difference, the DS package was shown to be superior over the SB package in the power cycling analysis.

Chip-scale packaging of power devices and its application in integrated power electronics modules

A power electronics packaging technology utilizing chip-scale packaged (CSP) power devices to build three-dimensional (3-D) integrated power electronics modules (IPEMs) is presented in this paper. The chip-scale packaging structure, termed die dimensional ball grid array (D/sup 2/BGA), eliminates wire bonds by using stacked solder joints to interconnect power chips. D/sup 2/BGA package consists of a power chip, inner solder caps, high-lead solder balls, and molding resin. It has the same lateral dimensions as the starting power chip, which makes high-density packaging and module miniaturization possible. This package enables the power chip to combine excellent thermal transfer, high current handling capability, improved electrical characteristics, and ultralow profile packaging. Electrical tests show that the V/sub CE/(sat) and on-resistance of the D/sup 2/BGA high speed insulated-gate-bipolar transistors (IGBTs) are improved by 20% and 30% respectively by eliminating the device wirebonds and other external interconnections, such as the leadframe. In this paper, we present the design, reliability, and processing issues of D/sup 2/BGA package, and the implementation of these chip-scale packaged power devices in building 30 kW half-bridge power converter modules. The electrical and reliability test results of the packaged devices and the power modules are reported.

A Dimple-Array Interconnect Technique for Power Semiconductor Devices

ABSTRACTThis paper describes a wireless-bond interconnect technique, termed Dimple-Array Interconnect (DAI) technique for packaging power devices. Electrical connections onto the devices are established by soldering arrays of dimples pre-formed on a metal sheet. Preliminary experimental and analytical results demonstrated potential advantages of this technique such as reduced parasitic noises, improved heat dissipation, as well as lowered processing complexity, compared to the conventional wire bonding technology in power module manufacturing. Thermomechanical analysis using thermal cycling test and FEM were also performed to evaluate the reliability characteristics of this interconnect technique for power devices.

Electrothermal simulation of an IGBT PWM inverter

A recently developed electro-thermal network simulation methodology is used to analyze the behavior of a full-bridge, pulse-width-modulated (PWM), voltage-source inverter which uses insulated gate bipolar transistors (IGBTs) as the switching devices. The electro-thermal simulations are performed using the Saber circuit simulator and include the control logic circuitry, the IGBT gate drivers, the physics-based IGBT electro-thermal model, and the thermal network component models for the power device silicon chips, packages, and heat sinks. It is shown that the thermal response of the silicon chip determines the IGBT temperature rise during the device switching cycle. The thermal response of the device TO247 package and silicon chip determines the device temperature rise during a single phase of the 60-Hz sinusoidal output. Also, the thermal response of the heat sink determines the device temperature rise during the system start-up and after load impedance changes. It is also shown that the full electro-thermal analysis is required to accurately describe the power losses and circuit efficiency. >