Power Cycling Test Research Articles

Calibration methods and power cycling of double-side cooled SiC MOSFET power modules

Reliability analysis depends heavily on accurate measurements of junction temperatures for power semiconductors. It forms the foundation for precise reliability tests such as power cycling tests. One of the most established methods for junction temperature measurement in MOSFETs is the VSD(T) method. With the introduction of new module configurations such as the DSC (double-side cooled) module with cooling on both sides, conventional calibration methods for single side cooling require a critical review regarding their applicability. This article will highlight various calibration options and analyse them in regard to sensitivity and reproducibility for DSC modules. Subsequently, the most promising methods are evaluated experimentally. It was found that by heating the modules on both sides, a better temperature uniformity can be achieved than from single side heating alone. This allows to apply the VSD(T) method on DSC modules also during power cycling. A power cycling test with in situ mechanical force measurement was conducted to verify the results.

High temperature reliability of pressureless sintered Cu joints for power SiC die attachment

This paper presents a reliability study on pressureless sintered Cu joints for attaching SiC power devices (5 mm × 5 mm). The samples were prepared using an optimized sintering process which has been identified by evaluating the shear strength of die attachment joints attaching dummy Si dies. The reliability and thermal performance of sintered Cu die attachment joints was investigated and compared with high temperature lead free solder joints under active power cycling test of 30 to 150 °C. It was also evaluated by using a thermal shock test with a temperature swing of −50 to 175 °C and a dwelling time of 30 min at peak temperatures. Microstructure of the sintered/soldered die attachment joints were characterized by a range of methodologies before and after test. Results show that the pressureless sintered Cu die attachment joints have a power cycling reliability lifetime of at least 3 times longer than the high temperature Sn5Sb soldered die attachment joints, assuming a 20 % increase in thermal resistance as failure criterion. The pressureless sintered Cu joints also present a nearly unchanged thermal resistance in the original 40 k cycles. This is because continued densification takes place in the pressureless sintered joints during reliability test, trading off the effect of defects induced by thermo-mechanical stress in the assembly.

AC Power Cycling Test Setup and Condition Monitoring Tools for SiC-Based Traction Inverters

AC power cycling tests allow the most realistic reliability assessment by applying close to real stress to the device or module under test to meet functional safety standards, which is highly critical for traction applications. This paper presents a comprehensive guideline and shares critical know-how to develop a 120 KVA AC power cycling test setup for high-power Silicon Carbide (SiC) modules. As of today, traction applications can not generate an early warning signal for drivers to replace critical components on time. For this purpose, the suitable precursors for all dominant failure mechanisms are discussed, and the corresponding condition monitoring tools are proposed to monitor the device aging on power converters. These condition monitoring tools are integrated into the built-in desaturation protection circuit of the electric vehicle (EV) gate driver for low-cost, practical implementation. The on-resistance of all twelve switches is monitored online as a temperature-sensitive electrical parameter (TSEP) to measure the junction temperature of the devices. To avoid heavy processing load in the microcontroller, the out-of-order equivalent time sampling technique is developed for data sampling, which leads to a measurement error of less than 1.5%. In addition, the design considerations regarding common mode noise and aging effect on DESAT protection are investigated, and experimental findings are presented.

Improving the reliability of power modules through layered diffusion solder interconnects – Comparative study based on experiments and FE-simulation

The demand for reliable, lead-free and high temperature stable solder interconnects for power electronic application has increased in recent years. The die attach solder materials are exposed to higher electrical currents and temperatures due to advancing designs and wide band-gap semiconductors. The diffusion soldering material Sn-Cu-Sn with its high post processing melting temperature is a promising option for high temperature die attach interconnects. The aim of this work is to predict potential failure mechanisms in the die attach of automotive power modules due to simulation based thermo-mechanical analysis of the diffusion solder Sn-Cu-Sn layer and SAC. The FE-model is validated with experimental results from active power cycling tests. The simulation indicates a potential for lifetime increase by usage of layered diffusion solder. The created FE-simulation model could be used for simulation-based design for reliability to reduce material costs and development time.

Electrothermal power cycling of GaN and SiC cascode devices

This study investigates the power cycling tests of the GaN and SiC cascode devices to enable analysis of the alteration of their properties, such as case temperature, transfer characteristics, threshold voltage and leakage current once cycles complete. The highest increase in case temperature is seen in GaN cascode devices and more pronounced changes are seen in the drain current of these devices than that of the SiC devices as well. This is also the case in threshold voltage instability which is seen in the transfer characteristics of GaN devices whereas there is no change in their leakage currents. With respect to SiC cascode devices, the case temperature rise in the devices is around 25 °C and there is little increase in the leakage current after increasing the cycles, although there is a decreasing trend in their threshold voltages that can be linked to the temperature rise of the device while their transfer characteristics are invariant with increasing power cycles.

Accuracy estimation of low-current voltage drop method for junction temperature monitoring under DC power cycling

A thorough accuracy estimation of the well-known low-current voltage drop method is carried out in this paper. A high-performance infrared camera is utilized as the reference in a DC power-cycling test on a commercial IGBT power module. The result shows that the low-current voltage drop method produces generally a higher temperature than the actual, in particular at the bond wire's joint point. However, a simple compensation method with a linear function can be easily adopted to compensate the temperature difference. After compensation, the maximum error of temperature swing is 0.28 °C.

Thermal creep and fatigue failure of the sintered silver solder in a SiC-IGBT module under power cycling

In this work, the creep samples of sintered silver were prepared by the chemical reduction method. According to the creep testing results, the Anand constitutive model was established to demonstrate the creep characteristics of sintered silver within a certain temperature range. According to the finite element electro-thermal–mechanical coupling analysis, the cyclic creep characteristics of sintered silver solder in the SiC-IGBT module under power cycling were simulated. The results shows that the sintering pressure and temperature can greatly promote the integrity of sintered silver by enhancing inert-particle bonding strength, and the established Anand model can effectively describe the creep behavior of sintered silver. The predicted results from electro-thermal–mechanical simulation were in good agreement with the power cycling testing results under the same condition. The finite element-based creep fatigue model is effective in predicting the creep fatigue life of sintered silver solders.

Damage-Based Lifetime Modeling for Power Electronic Devices

Lifetime modeling is an essential tool for ensuring the reliability of systems. The purpose is to estimate the time before the power electronic device failure so that downtime can be reduced and costly failures can be avoided in industry. This paper will first quantify the cumulative damage in the power cycling test using Junction Temperature Swing and Maximum Junction Temperature, and then formulate the cumulative damage-based lifetime model of power electronic devices. This model assumes that the lifetime is linear to the inverse of the cumulated damage, and shows superior performance in experiments compared with the well-known LESIT model.

Study on Lifetime Modeling of IGBT Modules Considering Electric Frequency Influence Mechanism

Affected by the randomness of the wind speed, the output electric frequency (0 20Hz) of the rotor-side converter does not match the thermal time constant (about 100ms) of IGBT modules, which causes the different junction temperature stress. It leads that it is difficult for the traditional lifetime model to reflect the influence of multi-time constant thermal load and result in inaccurate reliability evaluation. Aiming at the characteristics of wind turbine-side converters bearing thermal loads with multiple time constants, this paper studies the influence mechanism of electric frequency on the reliability of IGBT modules through a multi-physics simulation model and power cycling tests, and an improved lifetime model considering the influence of frequency parameters is proposed. Finally, an example analysis of the reliability evaluation of the DFIG rotor side converter is carried out. This paper is intended for the health management of converter systems and is supposed to be in service reliably.

Reliability Improvement of 3.3 kV Full-SiC Power Modules for Power Cycling Tests With Sintered Copper Die Attach Technology

Reliability Improvement of 3.3 kV Full-SiC Power Modules for Power Cycling Tests With Sintered Copper Die Attach Technology

TIMs for transfer molded power modules: Characterization, reliability, and modeling

This work presents an integrated experimental–numerical method to characterize, model, and experimentally study the properties of transfer molded power modules, considering two different thermal interface materials (TIMs). More specifically, a thermal grease and a phase change material are considered. The aim is to select the most reliable solution by making analytical characterization and power cycling tests on the modules equipped with the two kinds of TIMs. Then, further reliability study is accomplished, in order to estimate the lifetime of the power module equipped with the best TIM, that is the phase change one. Finally, a finite-element numerical model is developed and correlated with experimental data.

On-Site Estimation of Thermal Resistance Degradation of Double-Sided Cooling (DSC) Power Modules Under Power Cycling Conditions

Double-sided cooling (DSC) power modules are increasingly used due to their superior cooling capability and low parasitic inductance. However, the DSC modules have multiple interconnections for heat dissipation, so it is challenging to accurately monitor the thermal resistance degradation of each interconnection under power cycling conditions. An estimation method considering the self-heating and thermal coupling effects of DSC power modules is proposed based on a traditional lumped RC thermal impedance network. The proposed method combining a recursive least squares algorithm with a thermal network model can well evaluate the thermal resistance of each interconnection and their variations on-site during power cycling tests. The lifetime of DSC power modules for power cycling tests could be overestimated if using the 20% increment in overall thermal resistance of DSC modules as a failure criterion.

Long-Term Lifetime Prediction of Power MOSFET Devices Based on LSTM and GRU Algorithms

Predicting the long-term lifetime of power MOSFET devices plays a central role in the prevention of unprecedented failures for power MOSFETs used in safety-critical applications. The various traditional model-based approaches and statistical and filtering algorithms for prognostics have limitations in terms of handling the dynamic nature of failure precursor degradation data for these devices. In this paper, a prognostic model based on LSTM and GRU is developed that aims at estimating the long-term lifetime of discrete power MOSFETs using dominant failure precursor degradation data. An accelerated power cycling test has been designed and executed to collect failure precursor data. For this purpose, commercially available power MOSFETs passed through power cycling tests at different temperature swing conditions and potential failure precursor data were collected using an automated curve tracer after certain intervals. The on-state resistance degradation data identified as one of the dominant failure precursors and potential aging precursors has been analyzed using RNN, LSTM, and GRU-based algorithms. The LSTM and GRU models have been found to be superior compared to RNN, with MAPE of 0.9%, 0.78%, and 1.72% for MOSFET 1; 0.90%, 0.66%, and 0.6% for MOSFET 5; and 1.05%, 0.9%, and 0.78%, for MOSFET 9, respectively, predicted at 40,000 cycles. In addition, the robustness of these methods is examined using training data at 24,000 and 54,000 cycles of starting points and is able to predict the long-term lifetime accurately, as evaluated by MAPE, MSE, and RMSE metrics. In general, the prediction results showed that the prognostics algorithms developed were trained to provide effective, accurate, and useful lifetime predictions and were found to address the reliability concerns of power MOSFET devices for practical applications.

Difference Between the PWM and Standard DC Power Cycling Tests Based on the Finite-Element Simulation

PWM power cycling, which has complex control strategies and high testing costs, received a lot of attention in recent years due to the test conditions are closer to the application of power modules than standard DC power cycling. Therefore, the root difference of the failure modes and lifetime of IGBT power modules between DC and PWM power cycling is the concern in this paper, based on the finite element simulation. For stimulating the PWM power cycling with high accuracy and fast speed, an IPWM power cycling is proposed and verified by a simple model. Then an electro-thermo-mechanical coupled model of a single chip is established for comparison. Mainly focus on the current distribution, temperature distribution and stress distribution. The current distribution comparison results show no difference while a higher temperature gradient is shown in PWM power cycling due to the additional switching losses. However, the stress distribution results show chip solder layer is still the main failure mechanism both in DC and IPWM power cycling. Therefore, a conclusion can be obtained that there is no difference in failure mechanism and lifetime between DC and PWM power cycling. And the same bond wire failure and similar lifetime of DC and PWM power cycling tests further verify this conclusion.

In Situ Full-Field Deformation Characterization of Power Module and FEA Model Calibration Based on Stereo Digital Image Methodology

Due to the increasing concern for the global climate problem, the electric vehicle has drawn considerable attention. The power module with high reliability is the key to the deployment and development of the electric vehicle. However, in-depth evaluations, such as the tedious power cycling, are generally required to verify the reliability of the power module prior to putting it into the field application. Therefore, to determine the failure mechanism and evaluate the reliability of the power module, the in situ full-field characterization with 3-dimensional (3-D) deformation under the field application is essential. Besides, the characterization results can also provide a reference for the finite element analysis (FEA) model and further assess the reliability of the power module. In this paper, the deformation mechanism and multi-physics simulation of the power module are comprehensively studied. To achieve the 3-D full-field characterization of the deformation, the stereo digital image correlation (DIC) methodology is proposed to measure the out-of-plane and in-plane deformation. Additionally, in order to validate the feasibility of the proposed method, an active power cycle test rig that periodically heats up the power module by its own dissipation losses is constituted by the introduction of a front-to-front converter. The experimental results show that the maximum deformation occurs on the central surface of the focused zone while the edge bears a minimum deformation. Comparative evaluation indicates that the maximal error between experimental and simulation results is within 5%, thus enable the effectiveness of the FEA simulation model.

New model of crack propagation of aluminium wire bonds in IGBT power modules under low temperature variations

In this paper, a new model for wirebond degradation during power cycling in IGBT power module is proposed. This model is based on experimental crack propagation analyses and on a plastic strain empirical law. For the experiments, two power cycling tests in switching mode under high voltage were carried out respectively with junction temperature swings of ∆ Tj=30°C and 40°C at a minimal temperature of Tj,min=55°C. The DUTs and the test conditions were chosen so that only degradations of chip top-side interconnections could occur. The on-state voltage (VCE) was measured online during the tests as an indicator of wire and metallization degradations, moreover, the samples were removed at different aging stages. The removed samples were cross-sectioned in order to observe the crack propagation evolution with cycling. Concerning the plastic strain law, we used results from literature giving the evolution of the plastic strain variation (∆εpl) with bond-wire contact crack growth. As results, this new lifetime prediction model based on a modified Paris's law for aluminium wire bonds fatigue of IGBTs shows a good fitting of the test results and is it can be used to predict the lifetime under other load conditions. Finally, the lifetime of tested IGBT modules are estimated and used to verify the effectiveness of the proposed model.

Comprehensive CMR to differentiate between fitness levels amongst veteran endurance athletes

Abstract Funding Acknowledgements Type of funding sources: Public Institution(s). Main funding source(s): British Heart Foundation. Background Myocardial fibrosis has been demonstrated to be highly prevalent amongst endurance athletes. However, it is unknown whether endurance athletes with a greater exercise capacity have an increased prevalence of fibrosis. Purpose To determine whether greater maximal exercise threshold is associated with increased myocardial fibrosis on cardiac magnetic resonance (CMR) in veteran endurance athletes. Methods 50 healthy veteran (aged > 50 years old) endurance athletes (cyclists/triathletes) who train >10 hours/week for >15 years underwent comprehensive CMR assessment and functional threshold power (FTP) cycling testing. Focal myocardial fibrosis was measured quantitively from late gadolinium enhancement (LGE) imaging. Diffuse myocardial fibrosis was identified using global native T1 mapping of mid-left ventricular (LV) slices whilst extracellular volume (ECV) was calculated using haematocrit on the same day as CMR. Statistical analysis between groups was performed using independent t-test for nominal values and chi-squared for ordinal values. Results Athletes were divided into high and low performance groups based on FTP assessment (median 240.8 Watts). High performance athletes were significantly younger with increased bi-ventricular size and reduced right ventricular ejection fraction (RVEF) at rest (Table 1). However, there was no statistical difference in focal fibrosis, ECV or native T1 between the groups. Conclusion Maximal effort capacity did not appear to influence the prevalence of cardiac fibrosis which may be related to alternative factors such as cumulative exercise exposure. However, higher performing athletes had increased bi-ventricular size, particularly affecting the more compliant right ventricle (RV). Further larger studies are needed to confirm these findings.

Power Cycling on Lateral GaN and β-Ga<sub>2</sub>O<sub>3</sub> Transistors

The load cycling capability of novel power semiconductors is an important aspect when estimating their lifetime in field service. The Power Cycling Test (PCT) is the standard test to evaluate the lifetime of a semiconductor device under thermo-mechanical stress. PCTs are typically performed at temperature swings (ΔT) much higher than common operating conditions, to obtain results within a reasonable time. In this work, the PCT capability of gallium nitride (GaN) and gallium oxide (Ga2O3) lateral transistors is investigated. The GaN devices were tested in two groups with different ΔT. The temperature of the devices was monitored using two different temperature sensitive electrical parameters (TSEPs) and the accuracy of both methods was evaluated by comparing the results with the temperature, monitored by using an infrared (IR) camera. For Ga2O3 devices, no data on potential TSEP exists so far, thus, the typical TSEP for silicon (Si), silicon carbide (SiC) and GaN were investigated for their applicability to Ga2O3 devices. While a PCT was conducted on the devices, the temperature was also monitored using an IR camera. The results of the comparison of TSEP and IR camera data showed, that the accuracy of the TSEP for GaN matched either the temperature of the hottest spot on the chip (VDS method), or the average chip temperature (VGS method). For the Ga2O3 devices no suitable TSEP could be obtained and only the IR camera was used for the temperature measurement. It revealed a very uneven temperature and thus, current distribution on the chip. Furthermore, both GaN and Ga2O3 devices exhibit an outstanding power cycling capability with no failure after completing several millions of cycles. Considering the difference in Young’s Modulus of Si, GaN and Ga2O3, the PCT performance of GaN on silicon devices and Ga2O3 devices should be inferior to silicon devices. Thus, both device types, the GaN transistors and the Ga2O3 transistors, showed a PCT capability much higher than expected.

Reliability of SiC MOSFET Power Modules under Consecutive H3TRB and Power Cycling Stress

Power semiconductor modules are subject to both thermo-mechanical stress and electro-chemical stress during field operation. Usually, those stressors are investigated separately and possible interaction of both degradation mechanisms is neglected. In this work, the effect of combined thermo-mechanical and electro-chemical stress is investigated by means of consecutive H3TRB and PCT testing. One test group had been subjected to power cycling before the H3TRB test was performed, while another test group had been exposed to H3TRB stress before the power cycling test. As a reference, devices without preconditioning were tested in both, H3TRB and power cycling and are also used to compare the H3TRB and power cycling performance of the SiC devices to similar silicon devices. The results show, that the SiC devices feature a significantly better H3TRB performance than comparable silicon devices, but are inferior in terms of power cycling performance. Furthermore, the results for both test groups of the combined tests indicate that the failure modes for the previously stressed devices were the same as for the pristine devices and no impact of either preceding stress on the devices' lifetime could be observed. Therefore, the results of this work suggest no interaction between both stressors, at least not for the devices used for this investigation.

Proven Power Cycling Reliability of Ohmic Annealing Free SiC Power Device through the Use of SmartSiC<sup>TM</sup> Substrate

The Smart CutTM technology enables the combination of a high quality single crystal SiC layer onto a low resistivity handle wafer (<5mOhm.cm), allowing device optimization as well as the reduction of device’s conduction and switching losses. On this new SmartSiCTM substrate, the sheet resistance of the back side contact after metal deposition, without anneal, is about 10x lower than the annealed back side contact on 4H-SiC. Schottky-barrier vertical structures thinned down to 250μm were prepared for power cycling tests (PCT) measurements. Up to 250 k cycles, the devices remained within the specifications of AQG324 for samples prepared from SmartSiCTM substrates. We are demonstrating here that in addition to a higher current rating (up to 20%), the SmartSiCTM substrate enables a device fabrication simplification by skipping the annealing of the back-side ohmic contact, without compromising either the back-side contact resistance or the assembly PCsec reliability.