Power Consumption Of CMOS Circuits Research Articles

Reducing the Effect of Carry Propagation on Spintronic Adders

Due to the exponential increase of transistor leakage currents, especially in the technologies lower than 90[Formula: see text]nm, the static power consumption has dramatically increased. So, it is regarded as one of the main problems of the CMOS circuits. The spintronic devices, such as magnetic tunnel junction (MTJ), have notable advantages including low-static power consumption, nonvolatility, high endurance, compatibility with the CMOS transistors and the possibility of fabrication in high scales. Hence, the hybrid MTJ/CMOS circuits are considerable options to mitigate the problem of high-static power consumption in CMOS circuits. In this paper, a nonvolatile and low-power hybrid MTJ/CMOS full adder is proposed for implementation of in-memory computing. The drawback of existing full adders is their low-speed and high-power consuming for MTJ switching, which terribly affect the performance of multi-bit adders using these full adders. In this work, a new full adder is designed by eliminating the MTJ and transistor related to the input carry bit and modifying the tree structure of the MTJ network associated with the other inputs. In the proposed full adder, the effect of carry propagation has drastically decreased and its power consumption is also improved.

Implementation and analysis of Leakage Reduction Techniques in 6T SRAM cell

Leakage power dissipation is the dominating parameter while calculating in total power consumption of CMOS circuits specially in SRAM cells at 90 nm technology. In modern System on chips (SOCs), SRAM plays an important role because 70 to 80 percent area of any SOC is occupied by memory. So it is important to take care of leakage power dissipation and delay of memory based circuits. In this research paper, SRAM cell with hybrid Sleepy Keeper and Stack approach is proposed to optimize both the above parameters. SRAM cell using hybrid Sleepy Keeper and Stack approach leakage power consumption is 49.9 percent less and its dynamic power dissipation is 28% to 53% less as correlated to other implemented approaches. Read delay and power delay product of SRAM cell with hybrid Sleepy Keeper and Stack approach is less as compared to SRAM cell with Sleepy keeper and SRAM cell using Variable body biasing approach but these parameters value are more as correlated to conventional 6T SRAM cell and SRAM cell using stack approach.

Minimum energy consumption for rate monotonic scheduled tasks

Limited battery power is a typical constraint in stand-alone embedded systems. One way to extend the battery lifetime is by reducing CPU power consumption. Because of the quadratic relationship between power consumption in CMOS circuits and CPU voltage, power reduction can be obtained by scaling down supply voltage, or dynamic voltage scaling. However, reducing supply voltage slows down CPU speed since supply voltage has a proportional relationship with CPU frequency. On the other hand, in any real-time embedded environment (especially hard real-time), timing constraints are critical. In this paper, we focus on dynamic energy reduction of tasks scheduled by rate monotonic (RM) algorithm in a hard real-time embedded environment. The RM algorithm preemptively schedules any set of periodic tasks by assigning higher priorities to frequent tasks. For any periodic task set that satisfies the CPU utilization bound, we determine the provably optimal scaling of the worst-case execution time of each task that consumes minimum dynamic energy while satisfying the utilization bound. As RM algorithm is widely used, we expect this work can lead to better energy reduction management and expectations.

HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures

Dual supply voltage design is widely accepted as an effective way to reduce the power consumption of CMOS circuits. In this paper, we propose a comprehensive design framework that includes dual- scheduling, dual- allocation, controller synthesis as well as layout generation. In particular, we address a problem of high-level synthesis with objective of minimizing power consumption of storage units and multiplexers using dual- ; this is made possible by utilizing timing slack that is left in the data-path after operation scheduling. We use integer linear programming (ILP) and also provide heuristic algorithms to solve the dual- register and connection allocation. The physical layout of dual-circuits has to separate power rails of and cells from each other. We propose a voltage island based placement algorithm to relieve this restriction and allow more flexibility of placement. In experiments on benchmark designs implemented in 1.08 V (with Vddl of 0.8 V) 65-nm CMOS technology, both switching and leakage power are reduced by 20% on average, respectively, compared to data-path with dual-Vdd applied to functional units alone. Detailed analysis of area and wirelength is performed to assess feasibility of the proposed method.

Algorithm‐level evaluation of DPA resistance to cryptosystems

AbstractPaul Kocher has proposed a cryptanalysis technique called differential power analysis (DPA), in which attackers derive secret information such as private keys from a statistical analysis of the power consumption by the target device. There is now a demand to evaluate the DPA resistivity of a cryptographic device before the device is actually created. In this paper, we focus on simulating DPA with high speed at algorithm level in upstream of the design process. Messerges used a power leakage model to obtain power consumption from Hamming weight for proof of high‐order DPA. However, the correctness of the model has not been verified. In this paper, we verify that difference of power consumption in DPA can be obtained from the power leakage model by investigating the cause of power consumption of CMOS circuits and transition probability of logic gates. The verification is performed by means of a circuit simulator. Next we describe a method of performing algorithm‐level simulation which calculates power consumption using the power leakage model. We illustrate the effectiveness of the method by applying it to DPA resistivity evaluation of DES implementation. © 2008 Wiley Periodicals, Inc. Electr Eng Jpn, 165(3): 37– 45, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/eej.20611

Power Distribution Techniques for Dual VDD Circuits

Extensive research has proposed the use of multiple on-die power supplies (VDD) for reducing power consumption in CMOS circuits. We present a detailed study and design techniques for power delivery systems in dual VDD CMOS circuits. We first show that the total current to be delivered by the voltage supplies is significantly reduced (by 27%-46%) in dual VDD circuits. This current reduction prompts various design strategies that can be employed to design the power delivery system. We describe issues that arise at the system, board and package levels and propose a high-level model for the same. We then provide a new placement driven approach for designing on-die dual VDD power grids. Compared to already existing methods, the dual VDD grids generated by our approach reduce the worst case and average voltage drop by up to 12.3% and 6.8% respectively with no area overhead and sometimes improving wire congestion. We also show that dual VDD circuits can afford lower on-die decoupling capacitance budgets.

POWER ANALYSIS OF VLSI INTERCONNECT WITH RLC TREE MODELS AND MODEL REDUCTION

The lumped capacitance model, which ignores the existence of wire resistance, has been traditionally used to estimate the charging and discharging power consumption of CMOS circuits. We show that this model is not correct by pointing out that MOSFETs consume only part of the energy supplied by the source. During this study, it was revealed that about 20% of the power is consumed in the wire resistance of the buffered global interconnect, when the interconnect is modeled with RC tree networks. The percentage goes up to 30 when RLC model is used indicating the importance of inductance in interconnect model for power estimation. For RLC networks, we propose a compact yet very accurate power estimation method based on a model reduction technique.

Algorithm Level Evaluation of DPA Resistivity against Cryptosystems

Paul Kocher has proposed a cryptanalysis technique called Differential Power Analysis (DPA), in which attackers derive secret information such as private keys from a statistical analysis of the power consumption by the target device. There is now a demand to evaluate the DPA resistivity of cryptographic device before the device is actually created. In this paper, we focus on simulating DPA with high speed at algorithm level in upstream of the design process. Messerges used Power Leakage Model to obtain power consumption from Hamming Weight for proof of high-order DPA. However, the correctness of the model has not been verified. In this paper, we verify that difference of power consumption in DPA can be obtained from Power Leakage Model by investigating the cause of power consumption of CMOS circuits and transition probability of logic gates. The verification is performed by means of a circuit simulator. Next we describe a method of performing algorithm level simulation which calculates power consumption using Power Leakage Model. We illustrate the effectiveness of the method by applying it to DPA resistivity evaluation of DES implementation.

Power Estimation and Power Noise Analysis for CMOS Circuits

Power consumption is a primary concern for today's IC designers. However, determining an IC's power consumption is a difficult task, as consumption varies according to input stimulus conditions. This paper will focus on (1) the principal phenomena involved in the power consumption of CMOS circuits, (2) a brief survey of power estimation techniques, and (3) the effect of power-supply noise on circuit performance plus possible solutions to this problem.

Technique for reducing power consumption in CMOS circuits

With the advent of portable and high density microelectronic devices, the power dissipation of VLSI circuits is becoming a critical concern. A post-mapping technique is proposed that can reduce the power dissipation by performing gate resizing. Experiments performed on benchmark circuits have shown a power reduction in the range from 4.2 to 27.9% compared to circuits without resizing, with solutions obtained in a short computation time (no more than 8.5 s).

Estimating power consumption of CMOS circuits modelled as symbolic neural networks

The authors propose a new approach to the problem of estimating the average power consumption of a CMOS combinational circuit which is based on neural models. Given the gate level description of a circuit, they build the corresponding Hopfield neural network, store it, calculate the energy dissipated by the network and, finally, derive the power dissipated by the original circuit. All the operations above are executed in the symbolic domain, that is, algebraic decision diagrams are used to represent and manipulate the graph specification of the neural network modelling the circuit. The approach is viable and computationally efficient. In addition, it produces power estimates which are, on average, as accurate as the ones computed by state-of-the-art power analysis tools.

The impact of cell library characteristics on area, speed and power consumption of CMOS circuits

Technology mapping is one of the major steps in the synthesis process of integrated circuits. Efficient algorithms have been proposed in the recent past to optimize the number of cells required to implement a given design, to increase its speed, and to reduce its power dissipation. However, not enough effort has been spent in studying the relationship between the quality of the circuit produced by the logic synthesis tool and the cell library used to perform the mapping. In this paper we present experiments on technology mapping that show how the design of the cell library can influence area, speed and power consumption of the synthesized circuit.