Interconnect Power Consumption Research Articles

Microcellular long-chain branched polyphenylene oxide (PPO) with excellent comprehensive properties and comprehensive analysis of its dielectric properties

High-frequency and high-speed communications impose stringent requirements on low-dielectric materials with exceptional comprehensive properties. The development of dielectric materials with low dielectric constants and low dielectric dissipation factors holds significant value in reducing interconnect delay, power consumption, and crosstalk in high-frequency communication. In this study, polyphenylene oxide (PPO), known for its excellent properties, was chosen as the base material. Modified PPO with a long-chain branched structure was prepared using the multi-epoxy modifier ADR-4468. The increase in molecular weight and the formation of a long-chain branched structure improved the thermal stability, flexural properties, and foamability of PPO. Introduction of low-dielectric air into the material was achieved through supercritical CO2 foaming, resulting in a series of microcellular PPO foams exhibiting low dielectric properties (with a dielectric constant as low as 1.12 and a dielectric dissipation factor as low as 0.000636). Concurrently, the dielectric properties of microcellular PPO foams were examined at 10 GHz, revealing that the foam’s dielectric properties were minimally impacted by the properties of the raw materials. Based on water absorption analysis, an improved equation for calculating the dielectric dissipation factor was proposed, comprehensively analyzing the influencing factors on the foam’s dielectric dissipation factor. The study unveiled that water absorption significantly affects the foam’s dielectric dissipation factor, and under high expansion ratios, water absorption’s impact on the dielectric dissipation factor exceeds that of air introduction. These microcellular PPO foams, possessing excellent comprehensive properties and low dielectric characteristics, hold promise for applications in the realm of high-frequency and high-speed communications.

Energy-Efficient High-Speed dynamic logic-based One-Trit multiplier in CNTFET technology

The appeal of portable electronics, embedded systems, and other smart devices has been steadily growing over time. The multi-valued logic (MVL) was primarily introduced to handle the interconnect issues in binary logic. The use of ternary logic reduces the circuit complexity, power consumption in interconnects, and total chip area. The carbon nanotube field-effect transistor (CNTFET) offers some significant features like low leakage power, equal hole and electron mobility, and modulation in threshold voltage by adjusting the diameter of the carbon nanotube (CNT). In this paper, a clocked dynamic and pass transistor logic-based ternary 1-trit multiplier circuit with only 28 transistors has been proposed. The proposed logic avoids the conventional approach of using logic gates, encoder/decoder, and multiplexers, which reduces the total device count to implement the multiplier. The reduced transistor count offers a reduction in power consumption, delay, power-delay-product (PDP), and energy-delay-product (EDP) in comparison to other state-of-the-art designs. Stanford 32-nm CNTFET model file and Synopsis HSPICE simulator have been used to carry out the simulations at a supply of 0.9 V. The proposed circuit shows a 34.16 %, 66.44 %, and 82.80 % reduction in power, PDP, and EDP as compared to the lowest power, delay, and PDP of the designs under consideration. The performance of the multiplier is evaluated under different temperatures, supply voltages, loads, and oxide thickness.

SBCT-NoC: Ultra Low-Power and Reliable Simultaneous Bi-Directional Current-Mode Transceiver for Network-on-Chip Interconnects

The performance of Network-on-Chip depends a lot on the routers and interconnect circuits used in them. The gradual movement of technology towards nanometer scales has increased the core abilities, leading to an increase in delays and interconnect power consumption. As a result, %60 of the total current chip power consumption is related to the interconnect circuits. This paper has presented a simultaneous Bi-directional current-mode transceiver (SBCT-NoC) with two modes of operation, transmitter, and receiver. Two transceivers connected at both ends of an interconnect can use two-way communication through the same link. The proposed transceiver can significantly reduce the delay and power consumption of Network-on-Chip interconnects and increase the reliability using differential logic. This paper has simulated the circuits using 32-nanometer technology while considering the crosstalk noise effect. The results show the considerable advantage of the proposed method compared to previous interconnected circuit methods.

Carrier Phase Recovery and Compensation in Analog Signal Processing Based Coherent Receivers

Analog coherent receiver (ACR) is an attractive alternative to ADC+DSP based coherent receiver for reducing the complexity and power consumption in near-future high-capacity coherent data center interconnects (DCIs). Carrier phase recovery and compensation (CPRC), which is one of the major operations in the coherent DCIs, is essential to compensate for the phase and frequency offsets between the lasers and phase noise of lasers. In this work, we present a CPRC architecture for ACR based DCIs. The proposed CPRC approach comprises a dual loop architecture for frequency and phase offset corrections. Detailed design, analysis, effects of non-idealities, and simulation results of the dual loop CPRC are presented. For our analyses, circuit-realizable parameters have been used and the CPRC can be implemented in advanced CMOS/FinFET/SiGe technology nodes. The presented analog CPRC technique, along with lowering the power consumption, reduces the complexity in 200 Gbps/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\lambda$</tex-math></inline-formula> coherent DCIs.

Thermal and Performance Efficient On-Chip Surface-Wave Communication for Many-Core Systems in Dark Silicon Era

Due to the exceedingly high integration density of VLSI circuits and the resulting high power density, thermal integrity became a major challenge. One way to tackle this problem is Dark silicon. Dark silicon is the amount of circuitry in a chip that is forced to switch off to insure thermal integrity of the system and prevent permanent thermal-related faults. In many-core systems, the presence of Dark Silicon adds new design constraints, in general, and on the communication fabric of such systems, in particular. This is due to the fact that system-level thermal-management systems tend to increase the distance between high activity cores to insure better thermal balancing and integrity. Consequently, a designing dilemma is created where a compromise has to be made between interconnect performance and power consumption. This study proposes a hybrid wire and surface-wave interconnect (SWI) based Network-on-Chip (NoC) to address the dark silicon challenge. Through efficient utilization of one-hop cross the chip communication SWI links, the proposed architecture is able to offer an efficient and scalable communication platform in terms of performance, power, and thermal impact. As a result, evaluations of the proposed architecture compared to baseline architecture under dark silicon scenarios show reduction in maximum temperature by 15∘C, average delay up to 73.1%, and energy-saving up to ∼3X. This study explores the promising potential of the proposed architecture in extending the utilization wall for current and future many-core systems in dark silicon era.

Sol–gel deposited xerogel, aerogel and porogen based porous low-k thin films: A comparative investigation

Low dielectric constant (Low-[Formula: see text]) films are used as inter layer dielectric (ILD) in nanoelectronic devices to reduce interconnect delay, crosstalk noise and power consumption. Tailoring capability of porous low-[Formula: see text] films attracted more attention. Present work investigates comparative study of xerogel, aerogel and porogen based porous low-[Formula: see text] films. Deposition of SiO2 and incorporation of less polar bonds in film matrix is confirmed using Fourier Transform Infra-Red Spectroscopy (FTIR). Refractive indices (RI) of xerogel, aerogel and porogen based low-[Formula: see text] films observed to be as low as 1.25, 1.19 and 1.14, respectively. Higher porosity percentage of 69.46% is observed for porogen-based films while for shrinked xerogel films, it is lowered to 45.47%. Porous structure of low-[Formula: see text] films has been validated by using Field Emission Scanning Electron Microscopy (FE-SEM). The pore diameters of porogen based annealed samples were in the range of 3.53–25.50 nm. The dielectric constant ([Formula: see text]) obtained from RI for xerogel, aerogel and porogen based films are 2.58, 2.20 and 1.88, respectively.

Low-Power Cooling Codes With Efficient Encoding and Decoding

A class of low-power cooling (LPC) codes, to control simultaneously both the peak temperature and the average power consumption of interconnects, was introduced recently. An $(n,t,w)$-LPC code is a coding scheme over $n$ wires that (A) avoids state transitions on the $t$ hottest wires (cooling), and (B) limits the number of transitions to $w$ in each transmission (low-power). A few constructions for large LPC codes that have efficient encoding and decoding schemes, are given. In particular, when $w$ is fixed, we construct LPC codes of size $(n/w)^{w-1}$ and show that these LPC codes can be modified to correct errors efficiently. We further present a construction for large LPC codes based on a mapping from cooling codes to LPC codes. The efficiency of the encoding/decoding for the constructed LPC codes depends on the efficiency of the decoding/encoding for the related cooling codes and the ones for the mapping.

Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC

Ensuring reliable data transmission in multicore System on Chip (SoC), which employs Network on Chip (NoC), is a challenging task. This task is well addressed by Error Correcting Codes (ECC) in on-chip as well as off-chip networks. ECC significantly improves reliability of NoC interconnects with area and power overhead. In this paper, we propose a novel Transient Error Correction (TEC) coding scheme for reliable low power data link layer in NoC to attain a high error correction capability with less hardware overhead. Performance of TEC scheme is evaluated with realistic traffic patterns and validated with simulation results. The proposed scheme has less residual errors than the Hamming product code enabling reliable transmission at lower link swing voltage. Further, the scheme reduces the power consumption of NoC interconnects up to 71% as compared to Hamming product code with a marginal increase in codec delay and thus router delay. TEC scheme performs well in high noise environment with no delay penalty associated with retransmission.

High performance, variation-tolerant CNFET ternary full adder a process, voltage, and temperature variation-resilient design

Multiple-valued logic (MVL) decreases interconnection requirement and power consumption by realizing more data transmission over an interconnection wire. This paper investigates the carbon nanotube field effect transistors (CNFETs) using in the design of a ternary full adder cell. The proposed design takes advantage of the exceptional properties of CNFETs such as setting the desired threshold voltages by adjusting the carbon nanotubes (CNTs) diameters. We use Synopsys HSPICE simulator with a 32 nm Stanford CNFET model to simulate the ternary adders. We evaluate and examine the proposed design under different operational conditions such as different supply voltages (V), and different temperatures (T). Also, we investigate the designs under process variations (P) sensitivity. The simulation results show that the proposed design reduces the delay and energy consumption by up to 3.7X and 1.2X compared to the best state-of-the-art methods while being tolerant to process, voltage and temperature (PVT) variations.

A Novel Laser Source Supply Scheme for Optical Network on Chip

With the increasing number of integrated processor cores on a single chip, the bandwidth, speed, and power consumption of electrical interconnect cannot meet the needs of researchers. As a new technology, optical interconnect has become an alternative scheme for electrical interconnection. However, the traditional supply strategy of laser power brings a lot of static power loss, which will become a factor that cannot be ignored in the development of optical interconnect. In this paper, we propose a dynamic laser source supply scheme based on the autoregressive integrated moving average model, which can reasonably adjust the laser source size by prediction. The simulation results show that our dynamic supply scheme can save more than 70% of the laser power compared with the static supply under the real application of the PARSEC flow benchmarks.

Edge effect aware low-power crosstalk avoidance technique for 3D integration

Metal wires and through silicon vias (TSVs) are frequently performance bottlenecks of 3D ICs due to their high capacitive crosstalk which can be reduced using coding techniques. In this work we show that existing TSV crosstalk avoidance codes (CACs) are impractical for real applications due to the edge effects in TSV bundles. Additionally, these 3D CACs do not reduce the metal wire crosstalk and dramatically increase the power consumption of 2D and 3D interconnects. This work presents a 3D CAC which overcomes previous limitations. The method is based on an intelligent fixed mapping of the bits of existing 2D CACs onto rectangular or hexagonal TSV arrangements. Simulation results, obtained by circuit simulations in combination with an electromagnetic field solver, show that existing 3D CACs only reduce the TSV crosstalk by a maximum of 9.4%, provide no optimization of the metal wire crosstalk and induce an increase in the interconnect power consumption by about 50%. In contrast, the presented technique requires less hardware and reduces the maximum crosstalk of modern TSV and metal wire buses by 37.8% and 47.6%, respectively, while leaving their power consumption almost unaffected. Alternatively, our technique can reduce the TSV and metal wire crosstalk peaks by 20.3% and 47.7%, respectively, while additionally providing a reduction in the TSV and metal wire power consumption by 5.3% and 21.9%, respectively.

Power-aware high level evaluation model of interconnect length of on-chip memory network topology

Interconnect power is the factor that dominates the power consumption on the on-chip memory architecture. Almost all dedicated wires and buses are replaced with packet switching interconnection networks which have become the standard approach to on-chip interconnection. Unfortunately, rapid advances in technology are making it more difficult to assess the interconnect power consumption of NoC. To resolve this problem, a new evaluating methodology for interconnect power evaluation based on topology of on-chip memory (IP-ETOM) is proposed in this paper. To validate this method, two multicore architectures 2D-mesh and triplet-based architecture (TriBA) are evaluated in this research work. The on-chip memory network model is evaluated based on characteristics of on-chip architecture interconnection. MATLAB is used for conducting the experiment that evaluates the interconnection power of TriBA and 2D-mesh.

Direct-Liquid-Evaporation Chemical Vapor Deposition of Nanocrystalline Cobalt Metal for Nanoscale Copper Interconnect Encapsulation.

In advanced microelectronics, precise design of liner and capping layers become critical, especially when it comes to the fabrication of Cu interconnects with dimensions lower than its mean free path. Herein, we demonstrate that direct-liquid-evaporation chemical vapor deposition (DLE-CVD) of Co is a promising method to make liner and capping layers for nanoscale Cu interconnects. DLE-CVD makes pure, smooth, nanocrystalline, and highly conformal Co films with highly controllable growth characteristics. This process allows full Co encapsulation of nanoscale Cu interconnects, thus stabilizing Cu against diffusion and electromigration. Electrical measurements and high-resolution elemental imaging studies show that the DLE-CVD Co encapsulation layer can improve the reliability and thermal stability of Cu interconnects. Also, with the high conductivity of Co, the DLE-CVD Co encapsulation layer have the potential to further decrease the power consumption of nanoscale Cu interconnects, paving the way for Cu interconnects with higher efficiency in future high-end microelectronics.

Efficient Coupling of an Antenna-Enhanced nanoLED into an Integrated InP Waveguide.

Increasing power consumption in traditional on-chip metal interconnects has made optical links an attractive alternative. However, such a link is currently missing a fast, efficient, nanoscale light-source. Coupling nanoscale optical emitters to optical antennas has been shown to greatly increase their spontaneous emission rate and efficiency. Such a structure would be an ideal emitter for an on-chip optical link. However, there has never been a demonstration of an antenna-enhanced emitter coupled to a low-loss integrated waveguide. In this Letter we demonstrate an optical antenna-enhanced nanoLED coupled to an integrated InP waveguide. The nanoLEDs are comprised of a nanoridge of InGaAsP coupled to a gold antenna that exhibits a 36× enhanced rate of spontaneous emission. Coupling efficiencies as large as 70% are demonstrated into an integrated waveguide. Directional antennas also demonstrate direction emission down one direction of a waveguide with observed front-to-back ratios as high as 3:1.

More is Less, Less is More

Molecular-scale Network-on-Chip (mNoC) crossbars use quantum dot LEDs as an on-chip light source, and chromophores to provide optical signal filtering for receivers. An mNoC reduces power consumption or enables scaling to larger crossbars for a reduced energy budget compared to current nanophotonic NoC crossbars. Since communication latency is reduced by using a high-radix crossbar, minimizing power consumption becomes a primary design target. Conventional Single Writer Multiple Reader (SWMR) photonic crossbar designs broadcast all packets, and incur the commensurate required power, even if only two nodes are communicating. This paper introduces power topologies, enabled by unique capabilities of mNoC technology, to reduce overall interconnect power consumption. A power topology corresponds to the logical connectivity provided by a given power mode. Broadcast is one power mode and it consumes the maximum power. Additional power modes consume less power but allow a source to communicate with only a statically defined, potentially non-contiguous, subset of nodes. Overall interconnect power is reduced if the more frequently communicating nodes use modes that consume less power, while less frequently communicating nodes use modes that consume more power. We also investigate thread mapping techniques to fully exploit power topologies. We explore various mNoC power topologies with one, two and four power modes for a radix-256 SWMR mNoC crossbar. Our results show that the combination of power topologies and intelligent thread mapping can reduce total mNoC power by up to 51% on average for a set of 12 SPLASH benchmarks. Furthermore performance is 10% better than conventional resonator-based photonic NoCs and energy is reduced by 72%.

More is Less, Less is More

Molecular-scale Network-on-Chip (mNoC) crossbars use quantum dot LEDs as an on-chip light source, and chromophores to provide optical signal filtering for receivers. An mNoC reduces power consumption or enables scaling to larger crossbars for a reduced energy budget compared to current nanophotonic NoC crossbars. Since communication latency is reduced by using a high-radix crossbar, minimizing power consumption becomes a primary design target. Conventional Single Writer Multiple Reader (SWMR) photonic crossbar designs broadcast all packets, and incur the commensurate required power, even if only two nodes are communicating. This paper introduces power topologies, enabled by unique capabilities of mNoC technology, to reduce overall interconnect power consumption. A power topology corresponds to the logical connectivity provided by a given power mode. Broadcast is one power mode and it consumes the maximum power. Additional power modes consume less power but allow a source to communicate with only a statically defined, potentially non-contiguous, subset of nodes. Overall interconnect power is reduced if the more frequently communicating nodes use modes that consume less power, while less frequently communicating nodes use modes that consume more power. We also investigate thread mapping techniques to fully exploit power topologies. We explore various mNoC power topologies with one, two and four power modes for a radix-256 SWMR mNoC crossbar. Our results show that the combination of power topologies and intelligent thread mapping can reduce total mNoC power by up to 51% on average for a set of 12 SPLASH benchmarks. Furthermore performance is 10% better than conventional resonator-based photonic NoCs and energy is reduced by 72%.

PDNOC: Partially diagonal network‐on‐chip for high efficiency multicore systems

SummaryWith the constantly increasing of number of cores in multicore processors, more emphasis should be paid to the on‐chip interconnect. Performance and power consumption of an on‐chip interconnect are directly affected by the network topology. Researchers have proposed various topologies to optimize these metrics. The efficiency can also be optimized by proper mapping of applications. Therefore in this paper, we propose a novel partially diagonal network‐on‐chip (PDNOC) design that takes advantage of both heterogeneous network topology and congestion‐aware application mapping. We analyse the partially diagonal network in terms of interconnect structure, area usage, power consumption, routing algorithm and implementation complexity. The key insight that enables the PDNOC is that most communication patterns in real‐world applications are hot‐spot and bursty. We implement a full system simulation environment using SPLASH‐2 benchmarks. Performance metrics of standard mesh, concentrated mesh, full diagonal mesh and four types of the proposed PDNOC are measured in terms of network latency, application execution time and energy delay product. Evaluation results show that on average, the proposed PDNOC designs provide up to 36% improvement in execution time over concentrated mesh, and 3.6× better energy delay product over fully connected diagonal network. PDNOC design with two adjacent PD networks is a better candidate for higher efficiency, while four PD networks provide better performance. Copyright © 2014 John Wiley &amp; Sons, Ltd.

Voltage Optimization of Power Delivery Networks through Power Bump and TSV Placement in 3D ICs

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

Interview

Dr Dingyou Zhang of GLOBALFOUNDRIES talks about her research interests and the paper ‘BMD Impact on Silicon Fin Defect at TSV Bottom’, page 954. Dr Dingyou Zhang As the semiconductor industry strived to scale according to Moore's Law, the conventional planar ICs encountered many physical, technological and economic bottlenecks. 3D integration technology, by stacking and connecting function blocks in a vertical fashion, promises to alleviate such bottlenecks and has been widely investigated in recent years. The potential benefits of 3D integration include multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. Performance improvement in 3D ICs is mainly due to reduction of interconnect length reducing interconnect delay and power consumption. Small form factor is achieved by stacking active device layers on top of one another. During my M.S. and Ph.D. I was working on several research topics related to 3D integration, including TSV thermal-mechanical reliability and a novel chip-to-wafer 3D integration approach. I joined GLOBALFOUNDRIES in 2013 and I am currently working on advanced packaging technologies in the office of the CTO, focusing on through-silicon via (TSV) technology. The TSV is an important enabling component in 3D integration; electrically connecting multiple strata of ICs using short vertical vias that pass through a thinned silicon wafer substrate in order to establish a connection between the active side and backside of the die. Compared to conventional wirebonding and flipchip stacking, TSVs enable high-performance, high functionality, compact heterogeneous systems with high data bandwidth and speed, and low power requirements by providing the shortest interconnect path and higher interconnect density, compactly. However, it is challenging to fabricate reliable TSVs and substantial research is being conducted on aspects including their design, processing materials, metrology development and thermal-mechanical reliability. We report a recently found silicon fin defect at TSV bottom which was identified as a killer defect. To examine the root cause of this defect, we explored different inspection options and finally developed an effective method to catch the defect post TSV deep reactive ion etch. This is compatible with inline inspection and can be easily verified by cross-sectioning the via. With this well-established inspection approach, we were able to further investigate various potential root causes of the defect, such as TSV density microloading, TSV location and photoresist residue impacts. After ruling out other effects, bulk micro defect (BMD) turned out to be a key root cause; based on both BMD simulation and experimental results. Thus a low BMD or non-BMD silicon substrate is recommended to reduce or eliminate this defect. The work provides a viable way to clear this roadblock for TSV manufacturability. This is a killer defect which is hard to detect due to its deep location at the bottom of high aspect ratio vias, it can cause yield loss and requires elimination. We have seen mechanical failures caused by this defect after assembling TSV chips. One example we show is a silicon fin defect at TSV bottom causing copper diffusion into silicon cracks in TSV vicinity, after wafer thinning and TSV backside reveal process. A desirable inspection point for using our SEM automatic process inspection is right after TSV etch. Post etch is the first step in which we found this silicon fin defect and it saves downstream manufacturing resources from processing defective TSVs. Post etch inspection results can be easily verified physically and correlated to silicon fin defects, since TSVs are not filled with metal yet. This inspection approach can be adopted after TSV etch and before photoresist ashing and clean, which has less Q time concerns than between TSV post etch clean and dielectric liner deposition. 3D integration is predicted to be a key technology to solve performance and cost problems of conventional IC fabrication in the ITRS roadmap, which will probably be based on TSV technology. Full 3D process flows have already been demonstrated with no major showstoppers from a design or process point of view. While cost reduction is still on the to-do list for high volume production, multiple equipment and material suppliers are focusing on optimising processes to lower costs. With a positive outlook for commercialisation, a strong demand for such future 3D IC applications including memories and processors is expected in the next few years.

Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels

Shorter global interconnects enable 3D NoC structures to offer higher performance, improved packaging density, and lower interconnect power consumption to CMPs and SoCs compared to their 2D counterparts. However, substantial challenges such as high peak temperatures, power densities and area footprints of vertical interconnects in each layer cannot be ignored. In this paper, a power and area efficient 3D NoC architecture based on power-aware Bidirectional Bisynchronous Vertical Channels (BBVC) is proposed as a solution to mitigate these challenges. Instead of using a pair of unidirectional channels for inter-layer communication, utilizing a dynamically self-configurable BBVC enables a system to benefit from low-latency nature of the vertical interconnects. In addition, based on the GALS implementation approach of the proposed channels, a forecasting-based dynamic frequency scaling technique for reducing the power consumption of the inter-layer communication is introduced. Simulation results show that the proposed architecture can reduce up to 47% through-silicon via (TSV) area footprint and up to 18% NoC power consumption with a slight performance degradation compared to a typical Symmetric 3D NoC.