Abstract
Analog coherent receiver (ACR) is an attractive alternative to ADC+DSP based coherent receiver for reducing the complexity and power consumption in near-future high-capacity coherent data center interconnects (DCIs). Carrier phase recovery and compensation (CPRC), which is one of the major operations in the coherent DCIs, is essential to compensate for the phase and frequency offsets between the lasers and phase noise of lasers. In this work, we present a CPRC architecture for ACR based DCIs. The proposed CPRC approach comprises a dual loop architecture for frequency and phase offset corrections. Detailed design, analysis, effects of non-idealities, and simulation results of the dual loop CPRC are presented. For our analyses, circuit-realizable parameters have been used and the CPRC can be implemented in advanced CMOS/FinFET/SiGe technology nodes. The presented analog CPRC technique, along with lowering the power consumption, reduces the complexity in 200 Gbps/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\lambda$</tex-math></inline-formula> coherent DCIs.
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