Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC

M Vinodhini,T K Ramesh,N S Murty

doi:10.1109/access.2020.3025770

M Vinodhini, T K Ramesh + Show 1 more

Open Access

https://doi.org/10.1109/access.2020.3025770

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Abstract

Ensuring reliable data transmission in multicore System on Chip (SoC), which employs Network on Chip (NoC), is a challenging task. This task is well addressed by Error Correcting Codes (ECC) in on-chip as well as off-chip networks. ECC significantly improves reliability of NoC interconnects with area and power overhead. In this paper, we propose a novel Transient Error Correction (TEC) coding scheme for reliable low power data link layer in NoC to attain a high error correction capability with less hardware overhead. Performance of TEC scheme is evaluated with realistic traffic patterns and validated with simulation results. The proposed scheme has less residual errors than the Hamming product code enabling reliable transmission at lower link swing voltage. Further, the scheme reduces the power consumption of NoC interconnects up to 71% as compared to Hamming product code with a marginal increase in codec delay and thus router delay. TEC scheme performs well in high noise environment with no delay penalty associated with retransmission.

Highlights

Deep technology scaling in VLSI manufacturing process leads to many critically challenging issues in VLSI circuit design
Codec power, codec area and latency, average latency, Network on Chip (NoC) router area, NoC router power and delay are compared with Single Error Correction (SEC) [33], Single Error Correction Double Error Detection (SECDED) [33], Hamming Product Code (HPC) [13] and MECCRLB [19] schemes which is used in NoC router and not with those schemes used in IPs or NI
Reliability and NoC interconnect performance are compared with HPC and MECCRLB, as the error correction capabilities of these coding schemes are higher when compared to SEC and SECDED

Summary

INTRODUCTION

Deep technology scaling in VLSI manufacturing process leads to many critically challenging issues in VLSI circuit design. Among the diverse solutions suggested to focus on transient errors in NoC interconnects, the most viable and powerful solution is to facilitate information redundancy [11], [12]. M. Vinodhini et al.: TEC Coding Scheme for Reliable Low Power Data Link Layer in NoC scheme and hybrid scheme [13]. Our motivation is to adopt an ECC scheme using S2S approach to provide transient error correction for NoC interconnects. We put forward a new Transient Error Correction (TEC) coding scheme for NoC interconnects which improves the data reliability at data link layer (i.e., S2S error control) of the NoC. We present a detailed analysis of the proposed coding scheme in terms of NoC interconnect power and delay, probability of the residual error and link swing voltage.

RELATED WORKS

EVALUATION AND RESULTS OF TEC CODING SCHEME

TEC CODING SCHEME BIT OVERHEAD EVALUATION

RELIABILITY EVALUATION

CONCLUSION