Power Circuit Research Articles

Design and Implementation of a Transmitter for IR-UWB Standard

In wireless communication, the Ultrawide Band (UWB) is a technique for achieving a higher data rate, low power consumption, and less complexity. Impulse Radio - Ultra-Wide Band (IR-UWB) uses the baseband signal technique, reducing circuit complexity and power consumption. This work proposes an IR-UWB transmitter block with low power and tunable bandwidth that meets the UWB regulations of LRP (Low-Rate Pulse) UWB. The transmitter proposed uses a time-interleaved architecture using 0.18um CMOS technology using Cadence Virtuoso, which consists of On Off Keying (OOK) Circuit for the four stages of a pulse generator that operates in 6.17GHz-9.10GHz. The width of the pulse is between 0.096ns to 0.162ns using a current steering inverter. The proposed transmitter block has an output swing of 30 mV at 1MHz input Pulse Repetition Frequency (PRF) and a maximum PRF of 1GHz, at a 1GHz pulse rate, the power consumption was measured to be 8.3 mW.

A 14-Bit, 12 V-to-100 V Voltage Compliance Electrical Stimulator with Redundant Digital Calibration.

Electrical stimulation is an important technique for modulating the functions of the nervous system through electrical stimulus. To implement a more competitive prototype that can tackle the domain-specific difficulties of existing electrical stimulators, three key techniques are proposed in this work. Firstly, a load-adaptive power saving technique called over-voltage detection is implemented to automatically adjust the supply voltage. Secondly, redundant digital calibration (RDC) is proposed to improve current accuracy and ensure safety during long-term electrical stimulation without costing too much circuit area and power. Thirdly, a flexible waveform generator is designed to provide arbitrary stimulus waveforms for particular applications. Measurement results show the stimulator can adjust the supply voltage from 12 V to 100 V automatically, and the measured effective resolution of the stimulation current reaches 14 bits in a full range of 6.5 mA. Without applying charge balancing techniques, the average mismatch between the cathodic and anodic current pulses in biphasic stimulus is 0.0427%. The proposed electrical stimulator can generate arbitrary stimulus waveforms, including sine, triangle, rectangle, etc., and it is supposed to be competitive for implantable and wearable devices.

Matlab-Simulink of photovoltaic system based on a two-diode model simulator with shaded solar cells

This paper proposes a photovoltaic system modeling and characterization software based on Matlab-Simulink in order to estimate the parameters and the characteristic and electrical behavior of a cell/module with respect to changes in environmental parameter regarding irradiance, temperature, and surface conditions (partial shading). The first objective is to find the parameters of the nonlinear I–V equation by adjusting the curve regarding three particular points: open circuit, maximum power, and short circuit. Given these three points, which are provided by all commercial module datasheets, the method finds the best I–V equation for the two-diode photovoltaic (PV) model, with the best series and parallel resistances estimates. The accurateness of the simulator is verified by applying the model to different manufacturer’s modules. Thanks to an interactive graphic interface, this software offers a great flexibility to PV professional and to researchers.

Active rectifier with a fixed modulation frequency and a vector control system in the mode of bidirectional energy flow

Goal. Creation of a vector control system with improved characteristics for an active rectifier-voltage source operating in the bidirectional energy flow mode with a with a fixed modulation frequency. Methodology. The physical prerequisites for the active rectifier - voltage source operation in the system of a medium-power frequency electric drive are considered. A vector control system with a fixed modulation frequency is constructed, the principles of forming the signals acting in it and the influence on its operation of the converter power circuit parameters and the power consumed by it are considered. Mathematical modeling of the converter with the developed control system in MATLAB/Simulink made it possible to verify the correctness of the operation of the power circuit and the control system. Results. A new structure of a vector control system operating with a fixed modulation frequency is proposed, and the performance characteristics of the circuit in a wide range of changes in the magnitude and sign of the output power are obtained. The advantages of the new control system over the existing ones are shown. Originality. The physical prerequisites for the functioning of the power scheme and the vector control system of the ARVS proposed by the authors with a fixed frequency of modulation, the principles of forming the signals operating within it are considered in detail. Practical significance. New structure of the vector control system operating with a fixed modulation frequency is proposed and the advantages of the new control system over the existing ones are shown.

Design of charging station and optimization of oscillation circuits for new energy vehicles

In order to ensure good charging performance of new energy vehicles, the charging station was designed and the relevant oscillation circuits were optimized. The function and structure of the charging station was determined, and through a hierarchical framework, not only the success rate factor could be corrected, but also a resonant converter was combined to achieve efficient charging over a wide battery voltage range. The linear charging management chip was adopted, which integrated high-precision constant voltage source, temperature monitoring, charging status display, and battery charging completion termination function. The changes in excitation current and switching frequency during the charging process were studied, and the optimization basis for the relevant circuits was determined. A trigger was added to the input end of the oscillator to filter the input signal, which improved the accuracy of the RC oscillator cycle. The clock reference oscillation circuit and stable voltage power supply circuit were optimized. In order to verify the effectiveness of the proposed electronic control design, a hardware platform for the test of DC output characteristics was built. The results indicate that the output voltage waveform can effectively meet the working requirements.

Thermo-sensitive electrical parameters of high-power IGBTs based on gate-emitter voltage measurement during switching delay intervals

High-power insulated gate bipolar transistors (IGBTs) are widely used for wind power conversion and electric traction. Accurate estimation of IGBT junction temperature and active thermal control improve the reliability of power converters in such applications. Among the various available methods for junction temperature estimation, thermo-sensitive electrical parameter (TSEP) based estimation is simple, fast and amenable to real-time implementation. Evaluation of many TSEPs (e.g. forward voltage, threshold voltage, peak dv/dt, peak di/dt etc.) require measurement of multiple electrical quantities in the power circuit and/or in the gate-drive circuit. The measurement systems need to have high precision and/or high bandwidth as well. Moreover, the quantities in the power circuit require isolated measurement systems. This paper explores possible new TSEPs, that could be obtained through a single measurement of low-voltage quantity, namely, the gate-emitter voltage. Since the gate-emitter voltage varies primarily during turn-on and turn-off delay intervals, these switching intervals and their parameters are studied over a wide range of operating conditions. Since many practical converters are expected to operate at an ambient temperature as low as −35 °C, the experimental study is carried out over a wide temperature range from −35 °C to 125 °C. Further, to ensure wider applicability of the findings of the study, four IGBTs of different makes are considered for the experimental investigations. The experimental results bring out four different parameters pertaining to turn-on delay and another four parameters pertaining to turn-off delay, which are potential TSEPs. Of these eight TSEPs, five of them can be evaluated based on measurement of gate-emitter voltage only, and four of these have not been reported in the literature previously. In addition, the experimental data are useful for development of temperature-sensitive device models for simulation, performance assessment and design of gate-drive circuit for different temperatures, and for temperature-sensitive compensation of inverter dead-time effect.

Study of the Complexity of CMOS Neural Network Implementations Featuring Heart Rate Detection

The growing popularity of edge computing goes hand in hand with the widespread use of systems based on artificial intelligence. There are many different technologies used to accelerate AI algorithms in end devices. One of the more efficient is CMOS technology thanks to the ability to control the physical parameters of the device. This article discusses the complexity of the semiconductor implementation of TinyML edge systems in relation to various criteria. In particular, the influence of the model parameters on the complexity of the system is analyzed. As a use case, a CMOS preprocessor device dedicated to detecting heart rate in wearable devices is used. The authors use the current and weak inversion operating modes, which allow the preprocessor to be powered by cells of the human energy harvesting class. This work analyzes the influence of tuning hyperparameters of the learning process on the performance of the final device. This article analyzes the relationships between the model parameters (accuracy and neural network size), input data parameters (sampling rates) and CMOS circuit parameters (circuit area, operating frequency and power consumption). Comparative analyses are performed using TSMC 65 nm CMOS technology. The results presented in this article may be useful to direct this work with the model in terms of the final implementation as the integrated circuit. The dependencies summarized in this work can also be used to initially estimate the costs of the hardware implementation of the model.

Some Practical Applications of Discretely Tunable Couplers’ Matrix Model

The findings of a research of the practical application of a previously developed model of a decametric waves discrete coupler are presented. Due to the high accuracy achieved in describing the transforming properties of Coupler in the operating frequency range, together with the apparatus of the theory of complex variables, in particular with the method of conformal maps of fractional linear functions, it was possible to solve a number of applied problems. A method for calculating the area of consistent loads of discretely tunable power circuits of arbitrary structure has been developed. For completeness of the result, the case of matching a generator with a complex value of internal resistance with a given quality (with an acceptable value of the traveling wave coefficient) has been considered. The proposed approach to matching assumes that for any possible antenna load there must be appropriate combinations of discretely tunable elements of the Coupler power circuit that ensure matching with a given quality. The design ratio for images of arbitrary circles and straight lines conformally mapped by a matching quadrilateral to a given complex domain (i.e., expressions for calculating the coordinates of the circle center and its radius, as well as coefficients of the equation of straight lines) has been obtained. Studies of the matching properties of various circuits implemented on discrete elements have been carried out. The results of this study are important when choosing the structural design of the Coupler power circuit. Calculation formulas are obtained that allow us to estimate the relative losses of active power in the Coupler power circuit. This contributes to the reasonable choice of the best configuration option from several, similar in quality matching, thereby avoiding complicated temperature settings of the circuit elements. An exhaustive search method of tuning the discrete contour of the Coupler has been proposed, which is extremely simple and does not require heavy calculations with matrices and complex numbers.

Design of current steering logic CMOS circuit

The current-mode CMOS technology has many positive identities, while traditional current-mode CMOS circuits designing methods is comparatively more complex than voltage-mode CMOS. In this paper, using threshold logic, a current-mode CMOS circuits designing method based on spectral techniques is proposed. The proposed method is capable of designing combinational logic current-mode CMOS circuits. The sequential logic current-mode CMOS circuits can also be designed with the designed combinational logic current-mode CMOS circuit. The designed circuit is steered only by current signals. By using both simulations and real circuit tests, we proved the effectiveness of the proposed circuit designing method. Using HSPICE simulations, the designed circuit is proven to have advantages including lower circuit power consumption and higher stability of the current through power supply compared with voltage-mode CMOS and other main current-mode CMOS circuits, and the designed circuits require less control signals than other major current-mode CMOS circuits.

Machine Learning Techniques to Evaluate the Approximation of Utilization Power in Circuits

The need for products that are more streamlined, more useful, and have longer battery lives is rising in today's culture. More components are being integrated onto smaller, more complex chips in order to do this. The outcome is higher total power consumption as a result of increased power dissipation brought on by dynamic and static currents in integrated circuits (ICs). For effective power planning and the precise application of power pads and strips by floor plan engineers, estimating power dissipation at an early stage is essential. With more information about the design attributes, power estimation accuracy increases. For a variety of applications, including function approximation, regularization, noisy interpolation, classification, and density estimation, they offer a coherent framework. RBFNN training is also quicker than training multi-layer perceptron networks. RBFNN learning typically comprises of a linear supervised phase for computing weights, followed by an unsupervised phase for determining the centers and widths of the Gaussian basis functions. This study investigates several learning techniques for estimating the synaptic weights, widths, and centers of RBFNNs. In this study, RBF networks—a traditional family of supervised learning algorithms—are examined. Using centers found using k-means clustering and the square norm of the network coefficients, respectively, two popular regularization techniques are examined. It is demonstrated that each of these RBF techniques are capable of being rewritten as data-dependent kernels. Due to their adaptability and quicker training time when compared to multi-layer perceptron networks, RBFNNs present a compelling option to conventional neural network models. Along with experimental data, the research offers a theoretical analysis of these techniques, indicating competitive performance and a few advantages over traditional kernel techniques in terms of adaptability (ability to take into account unlabeled data) and computing complexity. The research also discusses current achievements in using soft k-means features for image identification and other tasks.

Inexact radix-4 Booth multipliers based on new partial product generation scheme for image multiplication

Inexact computing, is a modern approach for the development of low power and high-performance digital circuits, which involves approximation stages to get the utmost accurate result and are very much applicable in some error-tolerant applications like image processing. Such applications are limited to human eyesight ability, which gives us the freedom to make the approximate output. In this manuscript, two inexact partial product generators, viz. IPPG1, IPPG2 are proposed for the design of radix-4 based 8 × 8 Booth multipliers IRBM1.1, IRBM1.2, respectively. Moreover, an inexact 4:2 compressor is also proposed to add such partial product bits generated by IPPG1 and IPPG2, and nomenclate them as IRBM2.1 and IRBM 2.2, respectively. IPPG1 and IPPG2 are designed by introducing errors in the Karnaugh’s map to reduce the circuit complexity and errors, respectively. Similarly, errors are introduced in the truth table of the exact 4:2 compressor to design a low power, high speed inexact 4:2 compressor. Error metrics estimation of such proposed inexact Booth multipliers and the state-of-the-art designs are performed using MATLAB and circuit performance parameters like area, computational delay and power dissipation are extracted using gpdk45 nm technology. While comparing, IRBM1.2 offers minimum error metrics than all other reported design so far. Moreover, in the circuit level prospect, IRBM1.1 consumes minimum power and IRBM2.2 is the fastest among its reported counter-parts. IRBM2.2 offers minimum power-delay-area (PDA) product over all of its reported counter-parts. For the validation of the proposed designs, an image multiplication, edge-detection using Sobel operator, and convolutional neural network-based application is incorporated and quality assessment parameters are measured using MATLAB.

Experimental Findings and Theoretical Explanations on Time-Varying Immunity of LCC-HVdc Inverters to Commutation Failure Caused by Sending End AC Faults

Our preliminary work has recently reported that even sending end ac faults may cause commutation failure (CF) in LCC-HVDC inverters. However, the time-varying immunity to this new CF phenomenon is unclear yet. Thus in this paper, the immunity to the CF versus varying fault initiation time is firstly revealed by systematical hardware-in-the-loop experiments with different fault types and properties considered. The experimental findings are: 1) For both inductive and resistive faults, the time-varying immunity for the line-to-line and single-phase line-to-ground faults is much more prominent than for the three-phase and double-phase line-to-ground faults. 2) For the inductive faults, the immunity increases in the order of the three-phase, double-phase line-to-ground, line-to-line, single-phase line-to-ground faults. For the resistive faults, the immunity decreases in the order of the three-phase, double-phase, single-phase line-to-ground, line-to-line faults. 3) The immunity for the inductive faults is much lower than for the resistive faults regardless of the three-phase, double-phase, single-phase line-to-ground, or line-to-line faults. Secondly, these findings are theoretically explained by developing equivalent dc circuit and inverter reactive power consumption analysis. Thirdly, some practical considerations are clarified as to the impacts of various complex factors on the time-varying immunity. Finally, the time-domain waveforms sufficiently validate the time-varying immunity.

A High-Efficiency Inverse Class-F GaN MMIC Power Amplifier With Compact Output Matching Network

This brief presents a high-efficiency inverse Class-F (Class-F-1) monolithic microwave integrated circuit (MMIC) power amplifier (PA) fabricated with 0.25-lm GaN-on-Si technology. The design is based on a compact output matching network (COMN), which consists of a harmonic control circuit (HCC), an L-section matching circuit and a bias line. In order to reduce the circuit area that make it suitable for monolithic integration, the HCC uses only three transmission lines to achieve the second and third harmonic control. In addition, the conventional quarter-wave bias line is replaced with a shorter, proper one. The proposed COMN simplifies the matching network while realizing Class-F-1 operation, which improves efficiency, output power and reduce chip size. The maximum power added efficiency of 64.5% is achieved at 3.0 GHz, with an output power of 38.4 dBm and a power gain of 10.3 dB.

Design of high efficient low power static logic circuit using SG FinFET

ABSTRACT The increasing demand of integration density improvement and battery-powered device efficiency reduced complementary metal-oxide semiconductor (CMOS) technology node. In the technology of CMOS, the components are mainly affected with leakage power, dynamic switching power, short circuit power, gate oxide tunneling leakage current, sub threshold leakage current, and so on. To reduce the above limitations, design of high efficient low power static logic circuit using shorted-gate (SG) fin field-effect transistor (FinFET) based INput DEPendent (INDEP) in 22 nm CMOS technology (SLC-SG-FinFET-INDEP-22 nm CMOS) approach is proposed in this manuscript. The better selection of inputs to proposed INDEP FinFETs model is used for reducing leakage power. The efficiency of the proposed SLC-SG-FinFET-INDEP-22 nm CMOS technique is analysed using delay, power, power delay product, and stability analysis using noise margin. Thus, the proposed SLC-SG-FinFET-INDEP-22 nm CMOS has attained 21.31%, 41.47% and 12.7% lower delay, 20.87%, 34.5% and 22.41% lower power and 4.5%, 25.7% and 32.11% higher speed than existing methods static logic circuit input-controlled leakage restrainer transistor in 22 nm CMOS (SLC-ICLRT-22 nm CMOS), static logic circuit using self-control leakage-suppression block in 22 nm CMOS technology (SLC-SCLSB-22 nm CMOS), and static logic circuit using computational digital low dropout in 22 nm CMOS technology (SLC-CDLDO-22 nm CMOS) methods, respectively.

FFC-NMR Power Supply with Hybrid Control of the Semiconductor Devices

The performance of FFC-NMR power supplies is evaluated not only considering the technique requirements but also comparing efficiencies and power consumption. Since the characteristics of FFC-NMR power supplies depend on the power circuit topology and on the control solutions, the control design is a core aspect for the development of new FFC systems. A new hybrid solution is described that allows controlling the power of semiconductors by switches (ON/OFF mode) or as a linear device. The approach avoids over-design of the power supply and makes it possible to implement new low power solutions constituting a novel design by joining a continuous match between the ON/OFF mode and the linear control of the power semiconductor devices.

Parallel algorithms for power circuits and the word problem of the Baumslag group

Power circuits have been introduced in 2012 by Myasnikov, Ushakov and Won as a data structure for non-elementarily compressed integers supporting the arithmetic operations addition and (x,y)↦x·2y\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$(x,y) \\mapsto x\\cdot 2^y$$\\end{document}. The same authors applied power circuits to give a polynomial time solution to the word problem of the Baumslag group, which has a non-elementary Dehn function.In this work, we examine power circuits and the word problem of theBaumslag group under parallel complexity aspects. In particular, weestablish that the word problem of the Baumslag group can be solvedin NC—\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ extemdash$$\\end{document}even though one of the essential steps is to compare twointegers given by power circuits and this, in general, is shown tobe P-complete. The key observation is that the depth of theoccurring power circuits is logarithmic and such power circuits canbe compared in NC.

Impact of Circuit Power on the Energy Efficiency of Massive Multiple-Input Multiple-Output (MIMO) Cellular Systems

Massive multiple-input multiple-output (MIMO) systems are designed to increase data capacity systems. However, there are growing social and economic concerns in developing these communication technologies. Energy efficient systems are desirable for these systems considering the costs and minimizing resources. Thus, the optimization of these approaches is significant in the advancement of green communication. This paper converges on the circuit power in modelling massive MIMO systems. Specifically, to apply various power consumption of the transceiver chains, to determine the desired power of the base station value for maximum energy efficiency, and to define the effects of a realistic circuit power consumption model in Massive MIMO systems. Mathematical models were developed, and the corresponding codes were simulated using MATLAB. Different processing schemes were also studied, namely, maximum ratio transmission/maximum ratio combining, and zero forcing for the perfect and imperfect single-cells scenario. In contrast, multiple cells consider different re-use factors. As observed, a low power wattage consumption of transceiver chains and base stations is desired to produce a more remarkable relative change in energy efficiency. Local oscillators' power usage is also recommended to be low wattage. Low-power systems utilize low energy consumption but not disregarding higher energy efficiency. Other factors in data throughput – bandwidth, transmit power, noise power spectral density, and path loss, can be studied to optimize energy-efficient massive MIMO systems.

SCAPS Numerical Analysis of Graphene Oxide /TiO2 Bulk Heterojunction Solar Cell Sensitized byN719 Ruthenium Dye

Solid-state dye-sensitized solar cells (SSDSC) have been fabricated using two different metal oxide materials, graphene oxide and titanium oxide, are used as hole and electron transport materials, respectively. The N719 dye ruthenium between the hole and electron transport materials to act as an absorber layer in your Go/N719dye/TiO2 solar cells. Through the SCAPS-1D simulation, it was found that the Go/N719dye/TiO2 solar cells have significantly improved the performance of the solar cells compared to the Go/TiO2 solar cells. Specifically, the short circuit current (Jsc) has increased from 0.17 mA/cm2 to 1 mA/cm2, the open circuit voltage (Voc) has increased from 0.2 V to 1 V, and the power conversion efficiency (η) has increased from 0.02% to 2.5%. Additionally, Various factors that can affect the performance of Go/N719 dye/TiO2 solar cells. It was found that the optimal dye thickness for achieving high short circuit current density, high power conversion efficiency, and high open circuit voltage is between 200nm and 300nm. Furthermore, the operating temperature of the solar cells also affects their performance. Increasing the operating temperature negatively affects the open circuit voltage and power conversion efficiency of the cells, while the short circuit current density is slightly enhanced. Finally, the efficiency of a solar cell can be affected by the type of metal used for the electrode and the type of semiconductor material used in the cell. In Ni and Cu electrodes solar cells ohmic contacts allow for efficient transfer of electrons, whereas Schottky barriers can impede electron flow and reduce efficiency in Mo and Ag electrodes solar cells .

Surface oxidized Ti3C2 MXene: Lead-free Cs2AgBiBr6 double perovskite solar cell efficiency enhanced by interfacial engineering

In this study, thermal oxidation method is followed to prepare surface oxidized titanium carbide (TiO2-Ti3C2) nanomaterial. Here, the formation of anatase phase TiO2 nanoparticles over the surfaces of Ti3C2 MXene is confirmed by UV–Vis, FT-IR, XRD and FE-SEM and HR-TEM studies. The TiO2-Ti3C2 MXene acts an interfacial layer in double perovskite solar cell that exhibits high open circuit voltage (Voc of 1.01 V), short circuit current density (Jsc of 2.64 mA/cm−2), fill factor (FF of 0.55) and power conversion efficiency (PCE of 1.35%) under ambient conditions. Hence, we suggest that this surface modified material will be useful for double perovskite photovoltaics applications.

Bioremediation of Contaminated Diesel and Bioelectricity Generation Using Marine Bacterial Consortium Integrated with Microbial Fuel Cell

Biodegradation is a commonly used method to treat seawater polluted by petroleum. In addition to its ability to selectively degrade pollutants, it is also important to investigate the effectiveness of degradation and the benefits of restoration. This study focused on selecting a group of bacteria that can degrade diesel from marine sediment. The bacterial consortium called MB11 was found to be the most effective in removing diesel, with a removal rate of 53.77 ± 0.59 %. The consortium MB11 consists mainly of 6 types of bacteria: Enterococcus faecalis, Proteus mirabillis, Pseudomonas aeruginosa, Raoutella planticola, Enterobacter soli and Oceanotoga teriensis. The effective bacterial consortium MB11 was integrated with the floating MFC for electricity generation. The maximal open circuit voltage (OCV) and power density (PD) of 676.88 ± 5.94 mV and 0.16 ± 0.02 W/m3, respectively. HIGHLIGHTS The diesel degrading bacterial consortium was enriched and selected from the marine sediment sample. The consortium can degrade the contaminated diesel in artificial seawater and generated the electrical energy. The maximal power density of 0.16 ±02 W/m3 was gained when diesel was remove. GRAPHICAL ABSTRACT