Post-oxidation Annealing Research Articles

Low interface state density of SiC-based metal–oxide–semiconductor structure formed with perchloric acid at 203 °C

The SiO2/6H-SiC(0001) structure can be fabricated by the immersion in perchloric acid at 203 °C. High and low frequency capacitance–voltage measurements show that the metal–oxide–semiconductor diodes possess a low interface state density of 1×1011 cm−2 eV−1 at 0.5 eV below the conduction band when postoxidation annealing (POA) treatment is performed at 950 °C in nitrogen. The interface state density increases to about three times when the POA temperature is increased to 1100 °C. The oxide fixed charge density after the POA treatment is less than 1.4×1011 cm−2.

Effects of postmetallization annealing on ultrathin SiO2 layer properties

Observation of both longitudinal optical and transverse optical phonons of ∼1.3 nm ultrathin silicon dioxide (SiO2) layers formed by immersion in nitric acid shows that the SiO2 density increases by 16% after postoxidation annealing (POA) at 900 °C. For the SiO2 layers without POA, postmetalization annealing (PMA) greatly decreases the SiO2 thickness from 1.3 to 0.2 nm, the effect of which is attributable to the reaction of aluminum with SiO2 to form a metallic mixture of aluminum oxide and Si. For SiO2 layers with POA, PMA decreases the SiO2 thickness to a lesser extent (from 1.4 to 0.9 nm), because of the suppression of aluminum diffusion into SiO2 due to its dense structure. PMA is found to decrease the interface state density but increase the leakage current density.

Significant Improvement of Inversion Channel Mobility in 4H-SiC MOSFET on (11-20) Face Using Hydrogen Post-Oxidation Annealing

Significant Improvement of Inversion Channel Mobility in 4H-SiC MOSFET on (11-20) Face Using Hydrogen Post-Oxidation Annealing

High-temperature post-oxidation annealing on the low-temperature oxide/4H-SiC(0001)

A silicon–oxide layer was deposited by a low-pressure chemical vapor deposition technique at temperatures as low as 400 °C for gate dielectric material of the 4H-SiC metal–oxide–semiconductor (MOS) capacitors. Interfacial properties such as the amount of effective charge (Neff), interfacial oxide trapped density (Dit) and hot-carrier tolerance of the 4H-SiC(0001) MOS capacitors were evaluated by simultaneous C–V measurement as a dependence of a post-oxidation annealing (POA) at temperatures ranging from 1000 to 1200 °C. It was found that the POA temperature dependence of the Dit was different from that of the Neff. On the other hand, the POA dependence of hot-carrier tolerance was similar to that of the Dit. In consequence, those interfacial properties were sufficiently improved and became stable above the POA temperature of 1100 °C, which corresponds to the softening temperature of SiO2 bulk.

Excellent effects of hydrogen postoxidation annealing on inversion channel mobility of 4H-SiC MOSFET fabricated on (11 2 0) face

Effects of hydrogen postoxidation annealing (H/sub 2/ POA) on 4H-silicon carbide (SiC) MOSFETs with wet gate oxide on the (112~0) face have been investigated. As a result, an inversion channel mobility of 110 cm/sup 2//Vs was successfully achieved using H/sub 2/ POA at 800/spl deg/C for 30 min. H/sub 2/ POA reduces the interface trap density by about one order of magnitude compared with that without H/sub 2/ POA, resulting in considerable improvement of the inversion channel mobility to 3.5 times higher than that without H/sub 2/ POA. In addition, 4H-SiC MOSFET with H/sub 2/ POA has a lower threshold voltage of 3.1 V and a wide gate voltage operation range in which the inversion channel mobility is more than 100 cm/sup 2//Vs.

Phosphorous implantation in silicon through thin SiO2 layers: Oxide damage and postoxidation thermal treatments

A significant increase of HF etching rate and mean surface roughness (monitored by atomic force microscopy) was observed after P ion implantation on thin thermal SiO2 films (150 Å). The dependence upon the ion fluence (in the range 3×1012–5×1013 ions/cm2) and energy (in the range 270–500 keV) was analyzed, together with the recovery effect of a postimplantation annealing in N2 atmosphere. Moreover, the impact of P implants on oxides grown by different sequences, considering postoxidation annealing in N2O or N2 atmospheres, was also studied. The effect of ion irradiation was investigated by thermally stimulated luminescence (TSL) above room temperature in order to obtain information on point defects present in the layers. The results showed that postoxidation annealing treatments in N2 atmosphere carried out not only after, but also before ion implantation, were particularly useful in order to lower the concentration of TSL active defects. This can be interpreted as a role of N2 annealing in favoring a structural rearrangement of the SiO2 layers.

Effect of post-oxidationannealing on the electrical properties of deposited oxide andoxynitride films on strained-Si0.82Ge0.18 layers

Silicon dioxide and oxynitride films have been deposited on strained-Si0.82Ge0.18 layers at a low temperature using tetraethylorthosilicate (TEOS), TEOS/O2 and TEOS/NO plasma. Effect of post-oxidation annealing (POA) time (at 700 °C) on theelectrical properties of the dielectrics have been studied. The border trap (Qbt) generation has been characterized usingthe hysteresis in high-frequency capacitance-voltage (C-V) characteristics.It has been observed that the interface trap charge density (Dit) and gate voltage shift (ΔVG) decrease with POA time. Under Fowler-Nordheim constant current stressing, the charge trapping behaviour and the amount of border trap charge density are found to be low in the case of TEOS/NO-plasma-deposited oxynitride films compared with TEOS- and TEOS/O2-plasma-deposited oxide films.

Role of H<sub>2</sub> in Low Temperature Post-Oxidation Anneal for Gate Oxide on 6H-SiC

Role of H<sub>2</sub> in Low Temperature Post-Oxidation Anneal for Gate Oxide on 6H-SiC

Improvement of charge trapping by hydrogen post-oxidation annealing in gate oxide of 4H–SiC metal–oxide–semiconductor capacitors

The effect of hydrogen postoxidation annealing (POA) on the reliability of gate oxide formed in 4H–SiC metal–oxide–semiconductor (MOS) capacitors has been investigated. Argon POA at 1200 °C and hydrogen POA were carried out over a temperature range of 400–1000 °C to improve the properties of 4H–SiC/SiO2 interface and thermal gate oxide. Interface state density Dit decreases as the temperature of hydrogen POA increases and saturates at 800 °C. Additionally, the characteristics of charge trapping in gate oxide against the electron injection was greatly improved by the hydrogen POA above 800 °C. Hence, we can conclude that the hydrogen POA at high temperature is effective for improving the Dit and reliability of gate oxide formed in 4H–SiC MOS devices.

Effect of post-oxidation annealing of the oxynitride onthe C-V and G-V characteristicsof Al/thin oxynitride/n-Si tunnel diodes

Ultrathin oxynitrides have several advantages over conventionaloxides of silicon. In this paper we report the resultsof ultrathin (2.7 nm) oxynitride films grown on n-Si by N2Oplasma-assisted oxidation at 200 °C. Theoxynitride is characterized by fabricating Al/thin oxynitride/n-Si tunnel diodes and measuring thecapacitance-voltage (C-V) and conductance-voltage (G-V)characteristics in the frequency range 10 kHz to 1 MHz. Thesetunnel diodes with `as-grown' oxide have shown a frequencydependence in C-V characteristics, indicating a high({>}1012 cm-2 eV-1) interface state density (Dit). The effect of series resistance on the accumulation capacitance of the tunnel diodes is also studied. The density ofinterface states ({D}it) is estimated from the G-V characteristics at 10 kHz. Annealing of these oxynitrides (calledpost-oxidation annealing (POA)) is found to have a profoundeffect on the interface state density (Dit) and fixedoxide charge density (Qf). The POA is carried out in thetemperature range 300-650 °C in ambient nitrogen for 20 min. The tunnel diodes with POA oxide showed littlefrequency dependence in the C-V characteristics; thisobservation is attributed to the reduction in the interfacestate density (~5×1011 cm-2 eV-1) dueto POA. The fixed oxide charge (Qf) has been evaluatedfrom the C-V characteristics. It is observed that Qfhas a minimum value (~2.2×1012 cm-2) when theoxynitride is annealed at 350 °C.

Dependence of strain at the (111)Si/SiO 2 interface on interfacial Si dangling-bond concentration

Thermal oxidation of Si intrinsically gives rise to the generation of defects at the Si/SiO 2 interface as a result of mismatch induced stress. In standard thermal (111)Si/SiO 2, the dominant paramagnetic defect observed by electron spin resonance (ESR) is the P b centre (interfacial ·Si≡Si 3). In the present study, the inherently incorporated as-grown P b density (∼4.9×10 12 cm −2) was significantly enhanced to various levels, up to 3.1×10 13 cm −2, by means of the previously unveiled method for P b creation through appropriate postoxidation annealing in H 2. This resulted, among others, in the observation of a P b dependent anisotropic broadening of the ESR signal, partially arising from dipolar interaction within the essentially two-dimensional spin system. Successful quantitative simulation by a computational model has enabled detailed analysis of the line broadening mechanisms. The simulations reveal concentration related variations in the strain broadening contribution indicating a growing relaxation of the interfacial stress with increasing [ P b]. The results are discussed in the light of the connection between defect generation and the relaxation of stress.

Effect of oxidation method and post-oxidation annealing on interface properties of metal–oxide–semiconductor structures formed on n-type 4H-SiC C(0001̄) face

The C(0001̄) face of silicon carbide (SiC) has superior properties such as a faster oxidation ratio and a smoother surface compared with the Si(0001) face. We have investigated the oxidation and post-oxidation annealing effects on the capacitance–voltage and the interface state density (Dit) of n-type SiC metal–oxide–semiconductor (MOS) structures formed on the C(0001̄) face. It was found that pyrogenic oxidation and hydrogen annealing above 700 °C reduced Dit near the conduction-band edge. The value of Dit at Ec−E=0.2 eV is 1×1012 eV−1 cm−2, which is comparable with that of the MOS structure formed on the Si(0001) face. However, the value of Dit around the deep level at Ec−E=0.6 eV is one order of magnitude higher than that of n-type MOS structures formed on the Si(0001) face. It is very important to reduce Dit at the deep level for a high-quality SiO2/SiC interface on the 4H-SiC C(0001̄) face.

Analysis on electrical properties of ultrathin SiO 2/Si(111) interfaces with an atomic force microscope

We investigated the distribution of tunneling current through ultrathin oxide films on Si(111) with an atomic force microscope (AFM) using a conductive tip. The oxides were grown in dry O 2 at 600°C with or without post-oxidation annealing. For the oxide without post-oxidation annealing, we observed high tunneling current in the vicinity of step edges, which could be attributed to localized interface states around the step edges, while we could not detect such localized states for the oxides with post-oxidation annealing in H 2. This is an evidence that the localization states are active interface states and therefore, they were terminated with hydrogen during annealing. These results were supported by the conventional current–voltage ( I– V) measurement on metal oxide semiconductor (MOS) capacitors with 1.5-nm-thick oxides, showing the larger current for the substrates with the higher step density. The tunneling current was drastically reduced after the post-oxidation annealing.

Enhancement in soft breakdown occurrence of ultra-thin gate oxides caused by photon effect in rapid thermal post-oxidation annealing

Soft breakdown properties affected by photon energy during rapid thermal post-oxidation annealing (POA) of ultra-thin gate oxide are investigated. Generally, breakdown can be classified into normal hard breakdown (HBD) and soft breakdown (SBD). It was found that the occurrence of HBD and SBD depends on the process and stress field. Samples with front and back sides illuminated by a tungsten–halogen lamp during rapid thermal POA were examined. We find that front side illuminated oxides show easier SBD than back side ones. These results indicate that the photon energy may not only enhance the strength of Si–O bonds to suppress the lateral propagation of breakdown spots, but also to localize defects to form a conductive path of the leakage current. The understanding of the photon effect in rapid thermal POA is useful for controlling the electrical properties of ultra-thin gate oxides.

Improvement of wet-oxidized AlxGa1−xAs (x∼1) through the use of AlAs/GaAs digital alloys

A comparison of the water vapor oxidation characteristics of AlAs, Al0.98Ga0.02As, and an AlxGa1−xAs digital alloy was performed. The AlxGa1−xAs digital alloy consists of periods of 49 monolayers of AlAs and 1 monolayer of GaAs and has an equivalent composition of x=0.98. Oxidation rates and the structural integrity of the three layers were compared. When oxidized in water vapor, the AlxGa1−xAs digital alloy and the AlAs have similar oxidation rates, both of which are twice as fast as the Al0.98Ga0.02As layer. Post-oxidation annealing of these samples at 450 °C showed severe delamination at the oxide/GaAs interface in the AlAs sample while the AlxGa1−xAs digital alloy sample was not damaged.

Determination of the Density and the Thickness of SiO2 Films Using Extremely Asymmetric X-Ray Diffraction

From a theoretical understanding of rocking curves of extremely asymmetric X-ray diffraction from silicon crystals on which SiO2 films were thermally grown, both of the density and the thickness of the films were determined. Inherent measurement errors due to properties of the substrate were eliminated by dividing the intensity of the diffracted X-rays from the substrate with the film by the intensity without the film. The measurement results of the density indicated that the range of structural imperfection in SiO2 films varies with the conditions of oxidation and post-oxidation annealing.

Electrical characteristics of ultrathin gate oxide prepared by postoxidation annealing in ND3

The electrical and reliability characteristics of ultrathin gate oxide, annealed in ND3 gas, have been investigated. Compared with a control oxide, which had been annealed in NH3, the ND3-nitrided oxide exhibits a significant reduction in charge trapping and interface-state generation. The improvement of electrical and reliability characteristics can be explained by the strong Si–D bond at the Si/SiO2 interface. This nitridation process of a gate dielectric using ND3 has considerable potential for future ultra-large-scale integration device applications.

Observation of a Non-stoichiometric Layer at the Silicon Dioxide – Silicon Carbide Interface: Effect of Oxidation Temperature and Post-Oxidation Processing Conditions

ABSTRACTThermal oxides were grown on n-type 6H-SiC(0001) at 1100 °C for 2 hrs in a wet oxygen ambient after the substrates were cleaned using the complete RCA cleaning process. Metal-oxide-semiconductor (MOS) diodes were then fabricated and subsequently cleaned under different annealing conditions, including re-oxidation-, NO-, and forming gas (10% H2 + 90% N2)-annealing at 950 °C for one hour. Measurements of the interface state densities (Dit) at room temperature showed that post oxidation annealing (POA) reduced the Dit values to a varying degree depending on the specific annealing condition. Annealing in NO and forming gas resulted in the largest reduction in Dit values.Oxides were grown at 950, 1100, and 1250 °C for varying amounts of time without receiving POA. A non-stoichiometric (SixC, x>1) transition layer adjacent to the SiO2/SiC interface has been observed by electron energy loss spectroscopy (EELS). The thickness of this layer was found to increase with oxidation temperature and was not observed at all for a thin oxide grown at 950 °C. The Dit values (close to the conduction band) for diodes with oxides grown at 950°C without POA were lower than the Dit values for the samples oxidized at 1100 °C with any of the POA treatments. While the thickness of the transition layer was found to be dependent on temperature, our results indicate that it is independent of oxide thickness. This transition layer may be associated with the high Dit values and low channel mobilities for SiC MOSFETs.

Effect of Post-oxidation Annealing on GaAs Oxides Grown by Liquid Phase Chemical-Enhanced Technique

The characteristics of GaAs native oxides grown by liquid phase chemical-enhanced oxidation technique followed by post-oxidation annealing are investigated. The refractive index of as-grown oxide films increases with increasing As/Ga ratio, which depends on many process factors such as temperature, oxidizing time and pH values of the aqueous solution. Regardless of high or low refractive index as-grown oxide films, their refractive index approaches 1.8 after post-oxidation annealing. A model is proposed to explain this observation. Crystalline β-Ga2O3 is present in the oxide when the oxide is annealed at temperatures above 600°C and when the annealing time exceeds 6h. The shrinkage of oxide film thickness has been found. 30% enhancement of breakdown field strength and an order of magnitude of reduction of leakage current have been also obtained.

The Effects of Post-Oxidation Anneal Conditions on Interface State Density Near the Conduction Band Edge and Inversion Channel Mobility for SiC MOSFETs

ABSTRACTResults are reported for the passivation of interface states near the conduction band edge in n-4H-SiC using post-oxidation anneals in nitric oxide, ammonia and forming gas (N2/5%H2). Anneals in nitric oxide and ammonia reduce the interface state density significantly, while forming gas anneals are largely ineffective. Results suggest that interface states in SiO2/SiC and SiO2/Si have different origins, and a model is described for interface state passivation by nitrogen in the SiO2/SiC system. The inversion channel mobility of 4H-SiC MOSFETs increases with the NO annealing.