Post-layout Simulation Research Articles

A 17 GHz inductorless low‐pass filter based on a quasi‐Sallen–Key approach

SummaryIn this paper, an evolution of the Sallen–Key biquad architecture is presented, suitable for applications at very high frequency. The pole of the buffer amplifier is exploited as one of the poles of the biquad, therefore overcoming the constraints it poses on the maximum resonance frequency that can be achieved. This allows designing low‐pass filters with cutoff frequencies above 10 GHz without using bulky inductors and with good linearity performance provided by the use of feedback. This approach has been exploited to design a biquad in a commercial SiGe BiCMOS technology with maximum of about 320 GHz. The biquad has been designed to provide a resonance frequency of 12 GHz and a quality factor Q of 1.9; postlayout simulations show a cutoff frequency in excess of 17 GHz, 15.75 mW of power consumption, an equivalent input noise below 1 Vrms, and −52 dB of total harmonic distortion (THD) for a 640 mVpp input signal, with a very limited area consumption.

Ultra-Low-Power Compact Neuron Circuit with Tunable Spiking Frequency and High Robustness in 22 nm FDSOI

Recent years have seen an increasing popularity in the development of brain-inspired neuromorphic hardware for neural computing systems. However, implementing very large scale simulations of neural networks in hardware is still an open challenge in terms of power efficiency, compactness, and biophysical resemblance. In an effort to design biologically plausible spiking neuron circuits while restricting power consumption, we propose a new subthreshold Leaky Integrate-and-Fire (LIF) neuron circuit designed using 22 nm FDSOI technology. In this circuit, problems of large leakage currents and device mismatch are effectively reduced by deploying the back-gate terminal of FDSOI technology for a tunable design. The proposed neuron is able to operate in two spiking frequency modes with tunable bias parameter setting of key transistors, and it results in complex firing behaviors, such as adaptation, chattering, and bursting, through varying bias voltages. We present circuit post-layout simulation results and demonstrate the biologically plausible neural dynamics. Compared with published state-of-the-art neuron circuits, the circuit dissipates ultra-low energy per spike, on the order of femtojoules per spike, at firing rates ranging from 30 Hz to 1 kHz. Furthermore, the circuit is proven to maintain a good robustness over process variation and Monte Carlo analysis, with relative error 3.02% at a firing rate of approximately 67.1 Hz.

Quad path, CG-CS resistive feedback LNA architecture for 25–35 GHz band

In this paper, a Quad Path Noise Cancellation (QPNC) Low Noise Amplifier (LNA)presented for 5G sub-band 25-35GHz using GPDK 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology; which is composed of Common Source (CS) & Common Gate (CG) stages with resistive feedback and current reuse at the output. QPNC is used to cancel the noise of common gate transistors, which leads to reduce the noise fig. (NF). Resistive feedback is used to tradeoff between the input matching, gain, and NF i.e. overall refining the Figure of Merit (FoM) of the circuit. Mathematical analysis of impedance matching, gain, noise transfer function, and NF have been done using the small signal model of QPNC-LNA. Simulation has been done on Cadence Virtuoso software using GPDK 45 nm CMOS technology. Pre layout simulation result shows the minimum value of gain is 13.38 dB at 30.9GHz while the maximum value is 14.12 dB at 25.87GHz and flat over the entire frequency range. S11 i.e. input reflection coefficient is ranging from −16.16 dB at 25.21GHz to −11.52 dB at 35GHz for 50 Ω input impedance matching. NF value ranges from 2.69 dB at 25.69GHz to 3.77 dB at 35GHz. The IIP3 value for the proposed QPNC-LNA is 5.3 dB. For the four corners SS, SF, FS, and FF, process corner simulation has been performed. Post-layout simulation results depict the maximum value of gain is 12.71 dB at 25.75GHz. NF value is varying from 2.88 dB to 4.02 dB while the input reflection coefficient is ranging from −10.12 dB to −14.13 dB for 10GHz bandwidth. The circuit consumes 17.53 mW power at 1.2 V under a DC current of 14.61 mA, FoM1 is 8.36 dB and FoM2 of the proposed LNA is 49.35 dB. The layout of the proposed LNA is having an area of 0.03026mm2.

Differential high gain transimpedance amplifier with –3dB-bandwidth extension

In this article, a three-stage transimpedance amplifier (TIA) is designed and optimized to convert the input current to the output voltage and amplify it. The amplifier consists of a single-to-differential cross-coupled modified RGC (Regulated Cascode) input stage. The proposed TIA adopts a gm-boosted technique in the input stage by adding an auxiliary circuit that increases the –3dB-bandwidth by about 580 MHz, which lowers the input impedance resulting in a high input pole frequency. Also, an fT doubler stage and a third stage with minimum power consumption for fT doubling (second stage) and increasing gain are used respectively. The area consumption is reduced by replacing the conventional fT doubler topology resistors with transistors. Both stages of designed amplifiers have a variable gain mechanism. In the post-layout simulation, the circuit has a variable gain mechanism and a gain of up to 99 dBΩ with a –3dB-bandwidth of 720 MHz and an input-referred noise of 11.42 PA/√Hz. The post layout simulation is performed in 180 nm CMOS technology. The circuit's core power consumption is 6.0624 mW and occupies 0.051 mm × 0.06136 mm of area.

A 38.5-fJ 14.4-ns Robust and Efficient Subthreshold-to-Suprathreshold Voltage-Level Shifter Comprising Logic Mismatch-Activated Current Control Circuit

This brief presents a robust and energy-efficient voltage level shifter (VLS) for wide-range conversion from the subthreshold to the suprathreshold regime. The proposed VLS contains a new logic mismatch detection circuit to address the exist contention current of the conversion stage. A power reducer circuit is introduced to increase the drivability of pull-up and pulldown devices in linear and cut-off regions and further energyconsuming improvement. The proposed VLS is simulated using a 0.18-lm process, the minimal convertible voltage is 0.2 V (deep subthreshold region) for the input signal. Post-layout simulation considering process voltage temperature (PVT) variations proves the proposed VLS outperforms previous designs in several aspects. The results report the consuming energy of 38.5 fJ per transition, a static power of 73.4 pW, and a delay of 14.4 ns when converting range is 0.4 V to 1.8 V. The proposed VLS occupies a 59.98-lm2 silicon area.

A High Peak-efficiency Cross-coupled Charge Pump with Low Input Voltage for Energy Harvesting System

A high-efficient, low-voltage cross-coupled charge pump is presented in this paper. To decrease the conduction loss, a cross-coupled charge pump is proposed based on two auxiliary dynamic inverters to increase the clock swing. Meanwhile, a clocking scheme is designed to eliminate the reversion power losses. Based on proposed scheme, a higher output voltage is achieved by a three-stage topology by cascading the single stage. The proposed architectures of both single and three-stage charge pump are implemented under a standard 180nm CMOS technology. The post-layout simulation exhibits a peak power efficiency of 86.89% and 78.6%, respectively. And Monte Carlo (MC) simulation results indicate the proposed scheme features strong robustness to process variation.

Optimization of Slew Mitigation Capacitor in Passive Charge Compensation-Based Delta–Sigma Modulator

In this paper we propose a scheme of optimizing the size of charge compensation (CC) capacitor in a delta-sigma modulator (DSM) using a passive charge compensation (PCC) based switched capacitor integrator (SCI). The slewing behavior of a PCC based SCI is analyzed in both integration phase (IP) and sampling phase (SP) to optimize the size of CC capacitor. The effectiveness of the proposed scheme is demonstrated by implementing a 2-1 cascaded DSM using PCC based SCI with optimized value of CC capacitor in 0.18-μm CMOS technology. The DSM operates at a frequency of 5-MHz and achieves a peak SNDR of 103.1-dB in the audio bandwidth of 20-kHz. The power consumption of DSM is 220-μW at a supply voltage of 0.85-V and it consumes 1.3 mm of area. Post-layout simulations show an improvement of 10.8-dB in the SNDR of DSM by using the optimized value of CC capacitor in PCC based SCI.

An ultra-wideband low noise amplifier with cascaded flipped-active inductor for cognitive radio applications

Cognitive radio (CR) is an ultra-wideband communication system with a 50 MHz to 10 GHz frequency band that intelligently optimizes the use of the available frequency spectrum using dynamic spectrum monitoring. This paper proposes a differential ultra-wideband low-noise amplifier using two cascaded flipped-active inductors (CASFAI-LNA). The structure of each CASFAI consists of two transistors (gyrator-capacitor) and a common gate pMOS in its feedback path. The use of the capacitor cross-coupling method increases the transconductance of the circuit, which in addition to improving the gain and the noise figure, reduces the current consumption of the circuit. In addition, the biasing of active inductors from the feedback path reduces the power consumption of the circuit. This circuit is designed and validated in Cadence using a 0.18 μm CMOS process. The post-layout simulation results show that in the whole desired bandwidth (CR frequency range), the input matching is better than −10 dB, the maximum power gain is higher than 10.6 dB, the minimum noise figure is 2.24 dB, the stability factor is higher than 2.8, and the maximum IIP3 is −2.3 dBm. The proposed LNA consumes 6.12 mW from a 1.8 V DC supply.

Ultra-low-power 4th-order cascoded flipped source follower filter for portable biological healthcare systems

For the processing of signals in battery-powered and portable biological healthcare systems, there is a huge requirement for low-pass-filter (LPF) architecture. However, it’s challenging to achieve low-power operation of LPF with improved figure-of-merit (FOM). This paper presents a 4th-order cascoded flipped source follower filter (CFSF) which consumes ultra-low power of 0.4 nW from 0.5 V supply. The proposed architecture has been designed in 180 nm technology using BSIM3V3 MOS models. The post-layout simulation result shows that the proposed architecture delivers a gain of −4.7 dB, bandwidth (BW) of 100 Hz, dynamic range (DR) of 57.141 dB, input referred noise (IRN) of 97 μVrms, Total harmonic distortion (THD) of −40.833 dB and FOM of 1.39 × 10−15 J. The proposed architecture occupies an area of 0.052 mm2. Further, the statistically determined values for gain, DR, and THD with 200 Monte Carlo samples indicate mean values of −7.594 dB, 48.482 dB and −48.335 dB with standard deviation values of 7.063 dB, 5.779 dB and 12.316 dB, respectively. The proposed CFSF LPF architecture can be used in portable as well as wearable biological healthcare systems.

A doubled transistor latch common-mode insensitive rail-to-rail regenerative comparator for low supply voltage applications

This paper presents a high-speed common-mode insensitive two-stage regenerative comparator designed for low supply voltage applications. The proposed comparator features a doubled transistor latch that enables rail-to-rail operation, which is pioneered to the best of the author's knowledge. The voltage swing of output nodes of the pre-amplifiers is limited to reduce the power consumption. This limitation boosts the regeneration speed of the doubled transistor latch. The proposed comparator realized by a standard 65 nm CMOS technology. The post-layout simulation results corroborate that the proposed comparator with 50 MHz sample rate and 0.6 V supply voltage dissipates 3.4 µW power, and occupies 168 µm2 area. Also, the offset voltage variation within the full common-mode range can be below 2 mV. In a worst-case scenario compared to the conventional single-stage comparator, the proposed comparator improves delay and energy efficiency by more than 80%. Considering its overall performance, this energy-efficient comparator is suitable for all low supply voltage applications, including Internet of Things (IoT), successive approximation registers analog-to-digital converters (SAR ADCs), and biomedical implants.

A 5.4 ps resolution TDC design with anti-PVT-variation mechanism using 90-nm CMOS process

ABSTRACT The resolution of time-to-digital converters (TDC) is one parameter that will define its efficiency. This research demonstrates a 5.4 ps TDC with anti-PVT-variation implemented in 90-nm CMOS technology. The proposed converter uses a two-step architecture. The first stage is a Buffer Delay Line (BDL) to acquire a wide dynamic range characteristic. The second stage that will provide a higher resolution is Vernier delay line which receives the start and stop signals from the edge detector. A PVT (process, voltage, temperature) corner detector is equipped in the proposed TDC to resist the PVT variation. The proposed TDC’s post-layout simulation results achieve a delay variation of 2 ps and a resolution of 5.4 ps, and an acceptable dynamic range of 890 ps. The INL and DNL attained a value of 0.8 and −1 LSB from the simulations. The proposed TDC attains the best FOM based on post-layout simulations with a value of 0.177, which makes it superior to all prior designs.

A 6th-Order Active-RC Channel-Select filter with automatic continuous tuning for wideband receivers

A sixth-order channel-select filter with automatic continuous tuning for wideband receivers is presented. To reduce the power consumption and improve the bandwidth of the filter a new structure to implement active-RC biquadratic cells has been proposed. Continuous frequency tuning of the filter is also carried out by a new tuning strategy. The layout of the presented 6th-order filter with tuning circuits, occupy 0.372 mm2 of die area. Post-layout simulations have been conducted in a standard 0.18 µm CMOS process and the results show that the filter achieves 60 MHz bandwidth. Moreover, the in-band integrated input referred noise is 175 µVrms and the filter achieves an IIP3 of 12.7 dBm while consuming 5.9 mA from a 1.5-V supply. The simulation results also prove that the automatic tuning technique is quite effective and the deviation of the cut-off frequency due to PVT variations is reduced by almost 43%.

A Current Monitoring and Over-Current Detection Circuit for Safe Electrical Stimulation

This brief presents an integrated solution to over-current protection in neuromuscular stimulators. The proposed approach provides fast detection of a single-fault condition, i.e., unintentional electrode short circuit or malfunction of the stimulator, thereby preventing prolonged high-intensity currents from flowing into tissues. In addition, a programmable current threshold enables the system to be also used for monitoring the stimulation intensity. The proposed solution was designed in a 180 nm high-voltage CMOS technology, and its functionality was verified by post-layout simulations in which the safety mechanisms were tested under fault conditions. The implementation only occupies an area of 0.286 mm, making it feasible to be embedded in fully integrated NMES stimulators while providing the required patient safety.

Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer

In the modern graphics processing unit (GPU)/artificial intelligence (AI) era, flip-flop (FF) has become one of the most power-hungry blocks in processors. To address this issue, a novel single-phase-clock dual-edge-triggering (DET) FF using a single-transistor-clocked (STC) buffer (STCB) is proposed. The STCB uses a single-clocked transistor in the data sampling path, which completely removes clock redundant transitions (RTs) and internal RTs that exist in other DET designs. Verified by post-layout simulations in 22 nm fully depleted silicon on insulator (FD-SOI) CMOS, when operating at 10% switching activity, the proposed STC-DET outperforms prior state-of-the-art low-power DET in power consumption by 14% and 9.5%, at 0.4 and 0.8 V, respectively. It also achieves the lowest power-delay-product (PDP) among the DETs.

Low-Cost Indirect Measurements for Power-Efficient In-Field Optimization of Configurable Analog Front-Ends with Self-X Properties: A Hardware Implementation

This paper presents a practical implementation and measurement results of power-efficient chip performance optimization, utilizing low-cost indirect measurement methods to support self-X properties (self-calibration, self-healing, self-optimization, etc.) for in-field optimization of analog front-end sensory electronics with XFAB 0.35 µm complementary metal oxide semiconductor (CMOS) technology. The reconfigurable, fully differential indirect current-feedback instrumentation amplifier (CFIA) performance is intrinsically optimized by employing a single test sinusoidal signal stimulus and measuring the total harmonic distortion (THD) at the output. To enhance the optimization process, the experience replay particle swarm optimization (ERPSO) algorithm is utilized as an artificial intelligence (AI) agent, implemented at the hardware level, to optimize the performance characteristics of the CFIA. The ERPSO algorithm extends the selection producer capabilities of the classical PSO methodology by incorporating an experience replay buffer to mitigate the likelihood of being trapped in local optima. Furthermore, the CFIA circuit has been integrated with a simple power-monitoring module to assess the power consumption of the optimization solution, to achieve a power-efficient and reliable configuration. The optimized chip performance showed an approximate 34% increase in power efficiency while achieving a targeted THD value of −72 dB, utilizing a 1 Vp-p differential input signal with a frequency of 1 MHz, and consuming approximately 53 mW of power. Preliminary tests conducted on the fabricated chip, using the default configuration pattern extrapolated from post-layout simulations, revealed an unacceptable performance behavior of the CFIA. Nevertheless, the proposed in-field optimization successfully restored the circuit’s performance, resulting in a robust design that meets the performance achieved in the design phase.

A Bipolar 3-Level High-Voltage Pulser for Highly Integrated Ultrasound Imaging Systems

This paper presents a design solution for a bipolar return to zero (RZ) 3-level high-voltage TX pulser for high performance portable ultrasound medical imaging systems. Designed to be integrated in the front end of a PMUT probe composed by a 64-channel array working in the 1-10 MHz frequency range, the pulser is compact and power efficient as it employs minimum number of power transistors while ensuring high transmitting linearity because of the implementation of the RZ state. The circuit presents programmable features such as variable delays and rise/fall times to be controlled independently through a digital interface and it dissipates only 4.5 mW to bias the PMUT in RX state while achieving a small Req (2.24 Y). Transistor level and post-layout simulations performed in a BCD-SOI 0.16-lm technology are reported to demonstrate the effectiveness of the approach.

A Compact 0.2-1.6 GHz 20 MHz-Bandwidth Passive-LNA Exploiting an N-Path 1:3 Transformer

A compact passive low-noise amplifier (pLNA) with an N-path 1:3 transformer is demonstrated. Consisting of only switches and capacitors, the N-path 1:3 transformer offers passive voltage gain and high-Q bandpass filtering in a smaller area than the step-up spiral transformer. The proposed 4-path 20 MHz-bandwidth pLNA realized in 55-nm CMOS occupies only a 0.09-mm active area and consumes 0.7-3.1 mW between 0.2 GHz to 1.6 GHz. The post-layout simulations show that the proposed pLNA achieves a 6.2-8.8-dB passive voltage gain, 2.31-3.68-dB noise figure (NF), 5.04-14.17-dBm in-band (IB) input-referred third-order intercept point (IIP3), and 24.52-27.16-dBm out-of-band (OOB) IIP3 at an 80-MHz offset.

A Simple Timing-skew Calibration using Flip-flops for Time-interleaved ADCs

This paper presents a simple timing-skew calibration circuit for time-interleaved ADCs. At the core of the skew calibration scheme lies a pair of D flip-flops to detect the sign of the relative timing between a channel clock and the reference clocks. The D flip-flops form a latch structure to detect the sign of timing skew. The detected sign of the timing skew is accumulated by counters and used to control shunt-capacitor- inverter variable delay lines to adjust the timing of the channel clocks. Although this scheme cannot remove the skew from mismatches after the timing comparison point, it should be able to reduce the bulk of the timing skew. The performance of the calibration circuit implemented using a 28 nm CMOS technology was verified by post-layout simulations.

Class AB Voltage Follower and Low-Voltage Current Mirror with Very High Figures of Merit Based on the Flipped Voltage Follower

The application of the flipped voltage follower to implement two high-performance circuits is presented: (1) The first is a class AB cascode flipped voltage follower that shows an improved slew rate and an improved bandwidth by very large factors and that has a higher output range than the conventional flipped voltage follower. It has a small signal figure of merit FOMSS = 46 MHz pF/µW and a current efficiency figure of merit FOMCE = 118. This is achieved by just introducing an additional output current sourcing PMOS transistor (P-channel Metal Oxide Semiconductor Field Effect Transistor) that provides dynamic output current enhancement and increases the quiescent power dissipation by less than 10%. (2) The other is a high-performance low-voltage current mirror with a nominal gain accuracy better than 0.01%, 0.212 Ω input resistance, 112 GΩ output resistance, 1 V supply voltage requirements, 0.15 V input, and 0.2 V output compliance voltages. These characteristics are achieved by utilizing two auxiliary amplifiers and a level shifter that increase the power dissipation just moderately. Post-layout simulations verify the performance of the circuits in a commercial 180 nm CMOS (Complementary Metal Oxide Semiconductor) technology.

A low jitter 50 Gb/s PAM4 optical receiver in 130 nm SiGe BiCMOS

This paper analyzed the causes of phase jitter in four-level pulse amplitude modulation (PAM4) optical receiver (ORX), and a modified architecture was proposed. An optimized shunt-feedback transimpedance amplifier was employed to suppress the random jitter caused by the noise of analog front-end, a three-lane limiting amplifier with inter-stage feedback was introduced to extend the bandwidth, and retimers aligning the edges of thermometer codes with an external clock were also incorporated. The ORX fabricated in 130 nm SiGe BiCMOS technology occupies an area of 1.125 mm2 while dissipating 630 mW. The preliminary measured results demonstrated that the phase jitter of the most significant bit (MSB) was less than 0.08 UI for 25 Gb/s NRZ data. Post-layout simulation results indicate that our ORX can correctly decode 50 Gb/s PAM4 signal under a supply voltage of 3.3 V, and the peak-to-peak jitters for the MSB and the least significant bit (LSB) are only 1.5 ps and 2.9 ps, respectively.