Positive Oxide Charge Research Articles

Process-Induced Variations of 10-nm Node Bulk nFinFETs Considering Middle-of-Line Parasitics

Process-induced variations of 10-nm node n-type FinFETs considering middle-of-line parasitics were investigated in terms of dc/ac performances using fully calibrated TCAD simulations. Variations of positive fixed oxide charge density at shallow trench isolation interface and source/drain (S/D) height influenced off-state and on-state performance variations, respectively, but slightly on RC delay variations. Fin width variations induced off-state performance and RC delay variations critically due to the fluctuation of short channel effects. But, fin height variations affected them slightly due to the preserved gate-to-channel controllability and the buffered effects by varying drain currents and gate capacitances in the same direction. Gate length, spacer length, and S/D length variations influenced dc/ac performance variations severely; 2-nm-length changes were barely acceptable to satisfy 10% RC delay margin. Thus, the process-induced variability parameters, including fin width, gate length, spacer length, and S/D length, should be controlled tightly under a few nanometers to reduce dc/ac performance variations of the FinFETs.

Interface Analysis of P-Type 4H-SiC/Al<sub>2</sub>O<sub>3</sub> Using Synchrotron-Based XPS

In this paper, the interface between Al2O3 and p-type 4H-SiC is evaluated using x-ray photoelectron spectroscopy (XPS) measurements. These studies are made on dielectric-semiconductor test structures with Al2O3 as dielectric with different pre-and post-deposition treatments. XPS measurements on the as-deposited samples with two different pre-surface cleaning have shown no formation of a SiO2 interlayer. However, after the post deposition rapid thermal annealing (RTA) at 1100 °C in N2O for 60s, a SiO2 interlayer is formed. The surface band bending was determined from Si 2p core level peak shifts measured using XPS. These results suggest that Al2O3 deposited on the p-type 4H-SiC have a net positive oxide charge which is complementary to that of n-type 4H-SiC. From these shifts it was found that the as-deposited RCA cleaned sample had an oxide charge of 5.6×1013 q/cm-2, as compared to standard cleaned samples, having 4.6×1013 q/cm-2. A further reduction in oxide charge was observed after annealing at 1100 °C in N2O, down to a value of 4×1013 q/cm-2.

Effect of Gate Oxide Thickness on Negative Bias Temperature Instability in p-Mosfet with Sion Gate Dielectrics

The major reliability issue of metal-oxide-semiconductor field-effect-transistor (MOSFET) had been mainly hot carrier injection (HCI) until the late 1990s. However, negative bias temperature instability (NBTI) has been focused on since late 1990s until now because both aggressive scaling-down of gate oxide thickness and nitrogen incorporation into gate oxide, which mitigate HCI, enhance NBTI severely [1-2]. Although the phenomenon of bias temperature instability (BTI) has been known for several decades, there is still no clear explanation regarding the roles of gate oxide thickness on NBTI degradation of p-MOSFETs. For example, N. Kimizuka et al. reported that NBTI lifetime in p-MOSFET with thin gate oxide is larger than that with thick gate oxide under equivalent oxide field stress in the range of 2.0 ~ 4.0 nm oxide thickness [3]. On the contrary, S. Mahapatra et al. reported that BTI could be enhanced in p-MOSFET with thinner gate oxide due to high diffusivity of H2 in gate poly [4]. Meanwhile, G. Pobegen et al. reported that NBTI were all the same in p-MOSFETs with gate oxide thickness of 5.6, 13.9 and 29.1 nm [5]. In this work, we tried to resolve conflicting experimental results reported in the literature: Since the reduction of gate oxide thickness will enhance electric field across gate oxide, the application of thinner gate oxide will deteriorate NBTI degradation such like threshold voltage shift (ΔVt) caused by charge generation. However, it also increases oxide capacitance, reducing the effect of generated positive charge which is one of the main sources for NBTI degradation. We fabricated p-MOSFET devices with SiON gate oxide and p+ poly-silicon gate stack in the commercial graded production line through conventional DRAM full processes. We evaluated p-MOSFETs with two different thicknesses of gate oxide: One is p-MOSFETs with thin gate oxide of 3.36 nm (‘thin PMOS’ hereafter), and the other is p-MOSFETs with gate oxide of 7.27 nm (‘thick PMOS’ hereafter). We evaluated NBTI degradation electrically by measuring the threshold voltage (Vt) before and after NBT stress for 1,000 seconds at 125 °C with Agilent 4156C. By means of stressing for 1,000 seconds without a break and by measuring just after stress, we could minimize undesirable variations caused by recovery. Data shown in Fig. 1(a) represent ΔVt caused by NBT stress of various gate voltages. In Fig. 1(a), the slope of ΔVt for thin PMOS devices is steeper than that of thick PMOS. However, if we redraw the same data of ΔVt as a function of oxide electric field (Eox), then we have the same ΔVtslope for both thin and thick PMOS devices regardless of gate oxide thickness, as shown in Fig. 1(b). NBTI has been known to be exponentially increased with oxide electric field [6], which expressed empirically as Eq. (1). Our NBTI data of both thin and thick PMOS have the identical B value of 0.69 cm/MV. Also, NBTI is generally known to be caused by both interface trap and positive oxide charge which were generated during the NBT stress [6]. The generated charges contribute to threshold voltage shift via Eq. (2). Therefore, the total increased charge density (ΔNtotal) can be written as Eq. (3). By using Eq. (3), the correlation between the increased trap density and the oxide field applied during the NBT stress test can be obtained from the data in Fig. 1(b), and the result is shown in Fig. 1(c), in which all data lay on the one straight line. This suggests that NBT stress with the equivalent oxide field causes the same amount of increased charges independent of gate oxide thickness. Therefore, Eq. (1) must be normalized by Coxto count this observation as Eq. (4). As shown in Fig. 2, it is remarkable that NBTI degradation becomes the minimum at the condition of Eq. (5). NBTI drops drastically down to the minimum point and then rises with the increase of gate oxide thickness, which accounts for the previous conflicting experimental results. In summary, we found that the total increased charge density of the devices subjected to NBT stress is same as long as the equivalent electric field is applied, regardless of gate oxide thickness. By modifying the empirical equation for ΔVt, we suggest that the optimal value of Tox can be selected for a given gate voltage and oxide field acceleration coefficient. This finding can be served as the new guideline on selecting gate voltage and gate oxide thickness to minimize the NBTI degradation both for process development and integrated circuit design. Figure 1

Bias Temperature Instabilities for High-kHfO2LTPS-TFTs With Dual Plasma Treatment

This study is the first to investigate different reliability mechanisms of high-performance low-temperature polycrystalline silicon thin-film transistors (TFTs) with a $\hbox {HfO}_{2}$ gate dielectric before and after dual plasma treatment (DPT) under various bias temperature instability (BTI) stresses. DPT samples under positive bias temperature instability (PBI) and negative bias temperature instability (NBI) stresses exhibited different degradation phenomena because of the negative polarity trapped oxide charges and positive fixed oxide charges (Si+), respectively. In addition, experimental data exhibited better reliability immunity for PBI stress than NBI stress after DPT. Furthermore, we raised the temperature to clearly observe the effect of the PBTI stress analysis for samples with and without DPT. Extracted measurement results showed distinct time evolutions of the interface state densities (Nit) for samples with and without DPT, revealing the different mechanisms of Nit generation with and without DPT. Finally, we proposed a novel reliability mechanism called the quasi reaction-diffusion model to explain the generation of $\Delta\hbox {N}_{\rm it}$ , which also explains the unclear phenomena of mobility boost.

Influence of thermal annealing on structural properties and oxide charge of LiNbO3 films

C-oriented polycrystalline lithium niobate (LiNbO3) films have been deposited on Si substrate by the radio-frequency magnetron sputtering method in an Ar atmosphere and Ar + O2 gas mixture. All as-grown LiNbO3 films manifested positive fixed oxide charge regardless of the sputtering conditions. Donor centers are formed in Si substrate because of diffusion of O2 molecules during sputtering process. Thermal annealing (TA) of the deposited films leads to increase in the surface roughness and grain size as well as formation of LiNb3O8 phase in the studied films. Also, TA resulting in the decline of positive oxide charge due to the diffusion of oxygen molecules into LiNbO3 films from air and out-diffusion from Si substrate.

Effect of Fixed Oxide Charges and Donor-Like Interface Traps on the Breakdown Voltage of SiC Devices with FGR and JTE Terminations

The influences of positive fixed oxide charges and donor-like interface traps on breakdown voltages of SiC devices with FGR and JTE terminations were studied. The breakdown voltages of devices with both FGR and JTE terminations were found to degrade when the level of fixed oxide charges overs 1×1012 cm-2 due to enhancement of junction curvature by fixed oxide charges. The introduction of donor-like interface traps at the interface shows similar behaviors as fixed positive charges, suggested that both fixed oxide charges and interface traps should be taken into account when one optimizes device designs and processes.

Efficiency Enhancement of Nanotextured Black Silicon Solar Cells Using Al2O3/TiO2 Dual-Layer Passivation Stack Prepared by Atomic Layer Deposition.

In this study, efficient nanotextured black silicon (NBSi) solar cells composed of silicon nanowire arrays and an Al2O3/TiO2 dual-layer passivation stack on the n(+) emitter were fabricated. The highly conformal Al2O3 and TiO2 surface passivation layers were deposited on the high-aspect-ratio surface of the NBSi wafers using atomic layer deposition. Instead of the single Al2O3 passivation layer with a negative oxide charge density, the Al2O3/TiO2 dual-layer passivation stack treated with forming gas annealing provides a high positive oxide charge density and a low interfacial state density, which are essential for the effective field-effect and chemical passivation of the n(+) emitter. In addition, the Al2O3/TiO2 dual-layer passivation stack suppresses the total reflectance over a broad range of wavelengths (400-1000 nm). Therefore, with the Al2O3/TiO2 dual-layer passivation stack, the short-circuit current density and efficiency of the NBSi solar cell were increased by 11% and 20%, respectively. In conclusion, a high efficiency of 18.5% was achieved with the NBSi solar cells by using the n(+)-emitter/p-base structure passivated with the Al2O3/TiO2 stack.

Novel silicon drift detector design enabling low dark noise andsimple manufacturing

The Silicon Drift Detectors (SDDs) have replaced simple diodes in demanding X-ray fluorescence applications like in element analysers capable of detecting light elements. The reason for this is that with similar collection area the SDDs have a much smaller output capacitance than diodes due to a much smaller anode size. Thus the SDDs provide much better Signal to Noise Ratio (SNR) at smaller signal levels than diodes. The small capacitance in SDDs is achieved by placing concentric rings around a miniature sized anode. These rings are biased such that inside the SDD's fully depleted bulk a radial electric field component is established guiding signal charges towards the anode.Problems complicating the design of SDDs are positive oxide charge and interface dark noise. The latter is caused when leakage current generated at depleted interfaces mixes with the signal charge. It has been shown previously that by utilizing a chain of resistors connected to SDD's p+ drift rings and intermediate n+ rings both of these problems can be solved but the resistor chain arrangement requires an additional process step, which may not be standardly available. The interface generated dark noise and the requirement for a resistor chain can be removed by implementing suitable gaps in the p+ rings or with a resistive spiral as well as by implementing an additional anode for the collection of interface leakage current. Such SDDs are, however, vulnerable to accumulation of positive oxide charge complicating the manufacturing and likely reducing the effective lifetime of the detector.We present an SDD design comprising a novel ring arrangement preventing the formation of interface dark noise, being resistant to positive oxide charge, and removing the need for a resistor chain. In this work the design and operation principle of the proposed SDD is presented. The operation of the proposed SDD has been evaluated on TCAD with cylindrically symmetric 3D process and device simulations.

Influence Sputtering Conditions on Electrical Characteristics of Si-LiNbO3 Heterostructures Formed by Radio-Frequency Magnetron Sputtering

Polycrystalline LiNbO3 films on (001)Si substrate were grown by radio-frequency magnetron sputtering process at different sputtering conditions. X-ray diffraction analysis showed that films formed in Ar environment (P = 5.0 × 10−1 Pa) having two-phase composition (LiNbO3, LiNb3O8) transformed into c-axes-oriented LiNbO3 films when Ar pressure declined up to P = 1.5 × 10−1 Pa. This induced an increase in positive oxide charge and coercive field due to formation of defects in the LiNbO3 layer. Using Ar + O2 reactive gas mixture led to decline in defect formation (positive oxide charge) and coercive field. Current-voltage and capacitance-voltage analyses demonstrated that barrier properties of the Si-LiNbO3 heterojunctions are affected by the plasma composition.

Fabrication, characterization and simulation of channel stop for n in p-substrate silicon pixel detectors

Silicon detectors made on p-substrates are expected to have a better radiation hardness as compared to detectors made on n-substrates. However, the fixed positive oxide charges induce an inversion layer of electrons in the substrate, which connects the pixels. The common means of solving this problem is by using a p-spray, individual p-stops or a combination of the two. Here, we investigate the use of field plates to suppress the fixed positive charges and to prevent the formation of an inversion layer. The fabricated detector shows a high breakdown voltage and low interpixel leakage current for a structure using biased field plates with a width of 20 μm. By using a spice model for simulation of the preamplifier, a cross talk of about 1.6% is achieved with this detector structure. The cross talk is caused by capacitive and resistive coupling between the pixels.

Comparison between N2 and O2 anneals on the integrity of an Al2O3/Si3N4/SiO2/Si memory gate stack

In this paper the endurance characteristics and trap generation are investigated to study the effects of different post-deposition anneals (PDAs) on the integrity of an Al2O3/Si3N4/SiO2/Si memory gate stack. The flat-band voltage (Vfb) turnarounds are observed in both the programmed and erased states of the N2-PDA device. In contrast, this turnaround is observed only in the erased state of the O2-PDA device. The Vfb in the programmed state of the O2-PDA device keeps increasing with increasing program/erase (P/E) cycles. Through the analyses of endurance characteristics and the low voltage round-trip current transients, it is concluded that in both kinds of device there are an unknown type of pre-existing characteristic deep traps and P/E stress-induced positive oxide charges. In the O2-PDA device two extra types of trap are also found: the pre-existing border traps and the P/E stress-induced negative traps. Based on these four types of defects we can explain the endurance characteristics of two kinds of device. The switching property of pre-existing characteristic deep traps is also discussed.

A study on the electrical characteristics of InGaZnO thin-film transistor with HfLaO gate dielectric annealed in different gases

The effects of dielectric-annealing gas (O2, N2 and NH3) on the electrical characteristics of amorphous InGaZnO thin-film transistor with HfLaO gate dielectric are studied in-depth, and improvements in device performance by the dielectric annealing are observed for each gas. Among the samples, the N2-annealed sample has a high saturation carrier mobility of 35.1cm2/Vs, the lowest subthreshold swing of 0.206V/dec and a negligible hysteresis. On the contrary, the O2-annealed sample shows poorer performance (e.g. saturation carrier mobility of 15.7cm2/Vs, larger threshold voltage, larger subthreshold swing of 0.231V/dec and larger hysteresis), which is due to the decrease of electron concentration in InGaZnO associated with the filling of oxygen vacancies by oxygen atoms. Furthermore, the NH3-annealed sample displays the lowest threshold voltage (1.95V), which is attributed to the increased gate-oxide capacitance and introduced positive oxide charges. This sample also reveals a change in the dominant trap type due to the over-reduction of acceptor-like border and interface traps, as demonstrated by a hysteresis phenomenon in the opposite direction. Lastly, the low-frequency noise of the samples has also been studied to support the analysis based on their electrical characteristics.

Novel Gate Oxide Process for Realization of High Threshold Voltage in 4H-SiC MOSFET

We found that threshold voltage (Vth) of a 4H-SiC MOSFET increases drastically by performing low temperature wet oxidation after nitridation in a gate oxide process. The increment of Vth depends on the wet oxidation conditions. Wet oxidation increases the interface trap density (Dit) at deep level of SiC bandgap and decreases positive charge density inside the gate oxide layer. The amount change of the interface traps and the positive charges in the gate oxide makes Vth higher without a decrease in the channel mobility. We improved the trade-off between Vth and effective carrier mobility (μeff) in the MOSFET channel, and realized a low specific on-resistance (Ron,sp) SiC-MOSFET with Vth over 5 V by using the newly developed process.

Investigation of Fixed Oxide Charge and Fin Profile Effects on Bulk FinFET Device Characteristics

The effect of positive fixed oxide charge (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</sub> ) on the electrical characteristics of bulk FinFET devices is investigated and newly addressed as a Fin scaling detractor. The aggressively scaled Fin width leads to abnormal subthreshold slope (SS) degradation in nMOS devices even with a long channel length, while pMOS is free of such degradation. This observation is reproduced and analyzed by a well-calibrated TCAD simulation deck with Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</sub> introduced. A new Fin profile suppressing the Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</sub> effect is proposed, and the benefits of the new profile are predicted in terms of variability reduction and mobility improvement, as well as Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</sub> immunity.

Effect of negative bias temperature instability induced by a low stress voltage on nanoscale high-k/metal gate pMOSFETs

The effect of a low stress voltage on the negative bias temperature instability degradation in a nanoscale p-channel metal–oxide–semiconductor field-effect transistor using high-k/metal gate stacks is investigated. The direct current–current voltage and carrier separation methods are used to separate the effects of electrons and holes. The results indicate that a high stress voltage generates positive oxide charges that degrade the device, but a low stress voltage generates negative oxide charges that induce the turn-around effect of the threshold voltage.

Effects of post-deposition annealing ambient on chemical, structural, and electrical properties of RF magnetron sputtered Y2O3 gate on gallium nitride

The influence of post-deposition annealing (PDA) ambient [O2, Ar, forming gas (FG; 95% N2–5% H2), and N2] on chemical, structural, and electrical properties of RF magnetron sputtered Y2O3 films on gallium nitride (GaN) had been investigated. X-ray photoelectron spectroscopy revealed that the bulk oxide annealed in different ambient was composed of Y–O and Y–N bonds while the interfacial layer (IL) was comprised of a mixture of Ga–O, Y–O, Ga–O–N, and Y–N bonding. It was also detected that oxygen trapping happened in the bulk oxide for all of the investigated samples but this oxygen trapping ensued until the region of IL for sample annealed in O2 ambient. The Y2O3 film subjected to PDA in N2 ambient was in amorphous structure as no Y2O3 phase was able to detect by X-ray diffraction (XRD). When PDA was performed in O2, Ar, and FG ambient, polycrystalline phase of Y2O3 was detected. Besides, XRD results also revealed β-Ga2O3 phase for all samples. A correlation between the chemical and structural results with metal–oxide–semiconductor (MOS) characteristics of Y2O3/GaN structure subjected to different PDA ambient has been established. Of these investigated samples, sample annealed in O2 ambient possessed the lowest leakage current and the highest electric field (∼6.6 MV/cm) at 10−6 A/cm2 due to the attainment of the lowest interface trap density, total interface trap density, and slow trap density as well as the presence of positive effective oxide charge.

Investigation of electron mobility in surface-channel Al2O3/In0.53Ga0.47As MOSFETs

We report on the mechanisms limiting the electron mobility in surface-channel Al2O3/InGaAs MOSFETs. The electron mobility was obtained using pulsed Id−Vg and split C–V measurements. The energy profile of the density of interface states along with the equivalent-surface density of fixed positive oxide charge were obtained from the modeling of the gate-to-channel capacitance versus gate voltage (Cgc−Vg) characteristic. The experimental Cgc−Vg characteristic was modeled using a self-consistent Poisson–Schrödinger solver, while the electron mobility was calculated using the Kubo–Greenwood formula with nonparabolic corrections. Even when taking into account the impact of fixed oxide charges, Al2O3/In0.53Ga0.47As interface states within the In0.53Ga0.47As energy gap and aligned with the conduction band and the impact of remote phonon scattering, the mobility calculations revealed that the Al2O3/In0.53Ga0.47As surface roughness was the dominant mechanism limiting the electron mobility at high inversion charge density. The values of surface roughness predicted from the combined modeling and experimental results were confirmed by atomic force microscopy measurements and the process step responsible for the increased InGaAs surface roughness was identified.

Band offsets of metal–oxide–semiconductor capacitor with HfLaTaO/HfSiO stacked high-k dielectric

Band offsets of the metal–oxide–semiconductor (MOS) capacitor with HfLaTaO/HfSiO stacked dielectric were investigated and determined in this work. First, equivalent-oxide-thickness (EOT) of HfLaTaO/HfSiO stacked dielectric was demonstrated to be around 1.0 nm. Then, a typical flatband voltage (Vfb) versus EOT plot was used to extract the work function (Φm) of Ta deposited on HfLaTaO/HfSiO stacked structure. Furthermore, the Φm of the Ta gate electrode deposited on HfLaTaO/interfacial layer stacked dielectric was estimated to be 4.25 eV. Since the optical energy bandgap (Egopt) is one of the most important physical parameters, the Egopt of HfLaTaO dielectric was extracted from the HfLaTaO/quartz substrate structure by optical absorption measurements. The results suggest that the Egopt of 5.5 eV for HfLaTaO dielectric was determined by extrapolating a linear part of the curve to the intercept on the energy axis. Moreover, the Schottky barrier height (ΦB) was extracted from the analysis of the temperature dependence of the gate leakage current from 298 to 398 K. The result shows that the estimated ΦB during gate injection in Ta/HfLaTaO interface is around 1.0 eV. Through the extracted values of Φm, Egopt, and ΦB, band offsets of MOS capacitor with a Ta/HfLaTaO/HfSiO/P-Si(100) stacked structure were obtained. Finally, the related degradation mechanisms of the HfLaTaO/HfSiO stacked dielectrics under constant voltage stress are presented. The interface trap density and oxide positive charges increase with increasing the injected charges and are not constant during negative bias stress.

Enhanced degradation of n-MOSFETs with high-k/metal gate stacks under channel hot-carrier/gate-induced drain leakage alternating stress

Enhanced degradation of n-MOSFETs with high-k/metal gate stacks under CHC/GIDL alternating stress is investigated. CHC stress generates negative oxide charges while GIDL stress generates positive oxide charges in the gate oxide near drain region. Theses oxide charges degrade device reliability, and degradation is enhanced when CHC stress and GIDL stress are applied alternatively. The degradation under CHC/GIDL alternating stress is due to the neutral traps and interface traps, and increases with the increase in frequency.

Translation from Schottky Barrier to Atomic Bridging-Type Surface Photovoltages in Cr-Aqueous-Solution-Rinsed Si(001) Wafers

The Cr(OH)3/n-Si Schottky-barrier-type AC surface photovoltage (SPV) in n-type Si(001) wafers fades away during long air exposure at room temperature and/or thermal oxidation at 100 °C for a short time (10 min), indicating a collapse of the Schottky barrier. At 100 °C, the AC SPV reappears with a longer duration time in n-type Si wafers, explaining the occurrence and growth of a negative oxide charge because of the formation of an atomic bridging (CrOSi)- or CrO2- network reported previously. At 200 °C, the AC SPV approaches a strong inversion state in n-type Si. In contrast, in p-type Si(001) wafers, the AC SPV decreases with oxidation duration time at 100 °C. At 200 °C, the AC SPV completely disappears in p-type Si. This result explains why a positive fixed oxide charge in p-type Si was compensated for by the growth of a Cr-induced negative charge [(CrOSi)- or CrO2- network]. This reverse interrelation gives evidence that the translation occurs from the Schottky barrier to the atomic bridging AC SPV, and thus the Cr-induced negative charge can be proved to be described as (CrOSi)- and/or CrO2- networks as well as (AlOSi)- or (FeOSi)- networks that were demonstrated previously.