Positive Gate Stress Research Articles

Threshold voltage instability in SiO2-gate semi-vertical GaN trench MOSFETs grown on silicon substrate

We analyze the threshold voltage stability under positive gate stress in semi-vertical GaN trench MOSFETs with silicon oxide gate insulator. The experimental results, obtained by a fast setup capable of recording the threshold voltage transient with stress time as low as 10 μs, indicate that positive gate voltage induces a trapping of electrons in oxide border traps. In addition, experimental data obtained at different temperature and recovery bias conditions suggest that trapping proceeds through tunneling, from the inversion channel in the p-GaN layer to the traps. Finally, we developed a mathematical framework to model such tunneling process that conceptually explains the origin of the strongly stretched trapping transients and the results were compared with some relevant references on positive bias temperature instability in Si and GaN based devices.

8 A, 200 V normally-off cascode GaN-on-Si HEMT: From epitaxy to double pulse testing

In this paper, we provide a comprehensive study on all aspects of development of normally-off multi-finger III-nitride HEMT on Silicon in cascode configuration. AlGaN/GaN HEMT epi-stack with in situ SiN cap was grown on 2-in. Silicon (111) using MOCVD, utilizing a 2-step AlN nucleation, step-graded AlGaN transition layer and C-doped GaN buffer. Depletion-mode HEMTs in winding gate geometry with a gate width of 30 mm were fabricated with thick electroplated metal contacts and an optimized bilayer SiN passivation. Devices were diced and packaged in TO254 with conducting epoxy and Au-coated ceramic substrate. These packaged D-mode HEMTs exhibited a threshold voltage (Vth) of −12 V, maximum ON current of 10 A, and a 3-terminal hard breakdown in excess of 400 V. Bare dies of D-mode HEMTs were then integrated with commercially procured silicon MOSFET in a TO254 package in cascode configuration to achieve Vth > 2 V, ON current of 8 A, and breakdown >200 V. The normally-off cascaded GaN HEMTs were subjected to various gate and drain stress measurements and were found to exhibit a Vth shift of 10 mV after 1000 s of positive gate (+5 V) stress. The input and output capacitances of the cascode devices were measured to be 1 nF and 0.8 nF, respectively. The 3rd quadrant operation was checked at 8 A on-state current level to reveal a lower voltage drop of 0.7 V. Finally, cascode HEMTs were subjected to double pulsed testing (DPT) using a half-bridge evaluation board. On and off rise times of 52 ns and 59 ns were obtained along with energy loss of 25 μJ and 20 μJ, respectively, for devices switched at 8 A, 100 V.

Evaluation of Trapping Behaviors in Forward Biased Schottky-Type p-GaN Gate HEMTs

In this work, we investigated the trapping behaviors in the Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) under positive gate bias using the current-transient method. By excluding the trapping effect introduced by the measurement voltages, the actual recovery curves of drain transient current under different gate filling voltages and temperatures were extracted. The impacts of electron trapping, hole injection, and electron–hole recombination on the threshold voltage instability can be effectively distinguished according to the results of drain current variations under different gate stresses. In addition, the dynamic drain leakage current was monitored to confirm the electron–hole recombination and optical pumping of trapped electrons. The properties of three electron traps can be obtained based on the time constant spectrum (TCS), and a database of the gate-trapping behaviors in the GaN-based devices was constructed. The combined results may provide a basis for a better understanding of the threshold voltage instability under positive gate stress in the p-GaN gate HEMTs.

Superjunction Reliability Analysis Under Extreme High Positive and Negative Gate Voltage Stress

High gate stress test is an extremely important part of power device reliability test. On this basis, a 650 V super junction device is designed and fabricated, conventional stress test including high temperature gate bias (HTGB), high temperature reverse bias (HTRB) test results show that the device possess good reliability. The degradation of performance parameters under extreme high gate stress (including positive and negative) and the corresponding mechanism is further studied. It is found that the main performance parameters of superjunction MOSFET (SJ-MOSFET) will change significantly when the gate voltage stress is greater than 70 V. Under the positive high gate voltage stress, the threshold voltage decreases significantly. Under the negative high gate voltage stress, the threshold voltage also shifted to the left. Comparing the device under the same value of positive and negative high gate stress, it is found that the degradation degree of the device under positive stress is far greater than that under negative stress. Theoretical analysis combined with experimental data believes that the two degradation mechanisms are different. For positive stress, tunneling electrons collide on their way to the gate electrode creating electron–hole pairs, and the holes are captured by traps. But for negative gate voltage, holes tunnel and serve as extra gate positive charge directly. The electron injection efficiency is much higher than hole injection efficiency. Besides, the n-type region is larger at the bottom of the gate. Simultaneously, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{C}$</tex-math> </inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}$</tex-math> </inline-formula> measurement is also taken to prove the hypothesis.

Capture and emission time map to investigate the positive VTH shift in p-GaN power HEMTs

In this paper, for the first time the threshold voltage instability of 100 V rated p-GaN power HEMTs is investigated by combined pulsed-IV measurements and capture and emission time (CET) maps, by investigating a remarkable time window of 9 decades, from 1 μs to 1000 s. After a statistical analysis to demonstrate the repeatability of the experimental results, pulsed IV characterization revealed the existence of a non-monotonic ΔVTH shift, as a function of the (positive) gate stress bias. To gain further insight on the positive threshold shift, CET map analysis has been carried out at different temperatures: the results provide relevant insight on the physical properties of the population of traps responsible for the VTH shift, most likely located at the AlGaN/GaN interface. In addition, the related capture and emission time-constant as a function of temperature are investigated, thus allowing to extract the activation energies for the trapping and de-trapping processes, and to propose a model for the trapping mechanisms.

Non-monotonic threshold voltage variation in 4H-SiC metal–oxide–semiconductor field-effect transistor: Investigation and modeling

We propose an analytical model to reproduce the non-monotonic instability of the threshold voltage in 4H-SiC MOSFETs submitted to a positive gate stress bias. Experimental analysis of the threshold voltage transients indicates that both electron and hole trappings take place in the gate dielectric or at the dielectric/semiconductor interface, responsible for a VTH increasing–decreasing–increasing pattern. At low/moderate stress fields (&amp;lt;7 MV/cm), the electron trapping kinetics responsible for a positive VTH shift are modeled by a rate equation considering a trapping-inhibition model, which explains the logarithmic degradation kinetics. In the high field regime (&amp;gt;8 MV/cm), we propose that electrons can tunnel through the SiO2, be accelerated by the high field, and generate holes through impact ionization (II) or anode hole injection. These holes are then trapped in the oxide, thus generating a negative VTH shift. This second process has an exponential time-dependency, as found through the analysis of the corresponding rate equations. The time constant of the positive VTH shift is evaluated as a function of stress voltage and temperature. The results indicate that the time constant is strongly dependent on the electric field (that accelerates electrons to generate holes), and not thermally activated, in agreement with theoretical considerations.

Influence of the carrier behaviors in p-GaN gate on the threshold voltage instability in the normally off high electron mobility transistor

Threshold voltage (VTH) instability has been studied in the as-fabricated p-GaN gated enhancement-mode high electron mobility transistors (p-GaN E-HEMTs) under a positive gate stress. A negative VTH shift (ΔVTH) obtained by dynamic measurement has been observed more severely when compared to the static one. The VTH deviation is attributed to the complicated influence of carrier transport behaviors in the p-GaN gate. The impacts of hole accumulation, trapping, and consumption on the VTH instability and drain current variation can be effectively distinguished according to the transfer characteristics obtained from the pulse I–V measurement. Moreover, the density of hole traps in the p-GaN gate is estimated to be around ∼2 × 1011 cm−2 by the capacitance–voltage measurement, and the energy level is calculated to be around EV + 0.62 eV by fitting the recovery curve of gate current after positive gate bias. This study focusing on the in-depth influence of different carrier behaviors on the gate performance can help with the understanding and further improvement of the dynamic instability and reliability of the GaN-based HEMTs.

Use of Bilayer Gate Insulator in GaN-on-Si Vertical Trench MOSFETs: Impact on Performance and Reliability.

We propose to use a bilayer insulator (2.5 nm Al2O3 + 35 nm SiO2) as an alternative to a conventional uni-layer Al2O3 (35 nm), for improving the performance and the reliability of GaN-on-Si semi vertical trench MOSFETs. This analysis has been performed on a test vehicle structure for module development, which has a limited OFF-state performance. We demonstrate that devices with the bilayer dielectric present superior reliability characteristics than those with the uni-layer, including: (i) gate leakage two-orders of magnitude lower; (ii) 11 V higher off-state drain breakdown voltage; and (iii) 18 V higher gate-source breakdown voltage. From Weibull slope extractions, the uni-layer shows an extrinsic failure, while the bilayer presents a wear-out mechanism. Extended reliability tests investigate the degradation process, and hot-spots are identified through electroluminescence microscopy. TCAD simulations, in good agreement with measurements, reflect electric field distribution near breakdown for gate and drain stresses, demonstrating a higher electric field during positive gate stress. Furthermore, DC capability of the bilayer and unilayer insulators are found to be comparable for same bias points. Finally, comparison of trapping processes through double pulsed and Vth transient methods confirms that the Vth shifts are similar, despite the additional interface present in the bilayer devices.

Trapping and Detrapping Mechanisms in β-Ga₂O₃ Vertical FinFETs Investigated by Electro-Optical Measurements

We present a detailed investigation of the trapping and detrapping mechanisms that take place in the gate region of $\beta $ -Ga2O3 vertical finFETs and describe the related processes. This analysis is based on combined pulsed characterization, transient measurements, and tests carried out under monochromatic light, with photon energies between 1.5 and 5 eV. The original results presented in this article demonstrate that: (i) when submitted to positive gate stress with ${V}_{\text{GS}} > 3$ V, the devices show a significant threshold voltage variation; (ii) this effect is not recoverable in 10 000 s in rest condition (zero bias, dark condition). (iii) ${V}_{\text{TH}}$ can quickly recover its initial value when the device is illuminated with UV-C light at 280 nm. (iv) Stress-recovery experiments carried out at different photon energies allowed us to estimate the threshold energy for the release of carriers from the Al2O3/Ga2O3 interface, and for the injection of electrons from metal to the Al2O3 insulator (conduction band discontinuity at the metal/Al2O3 interface).

Charge Buildup and Leakage Current in Gold/Parylene-C/ Pentacene Capacitor under Constant-Voltage Stress

Degradation of metal-insulator-semiconductor (MIS) capacitors of gold/Parylene-C/Pentacene under constant voltage stress (CVS) was investigated to explore the electrical stability and reliability of Parylene C as a gate dielectric in flexible electronics. A stress voltage of fixed magnitude as high as 20 V, both negative and positive in polarity, was applied to each MIS capacitor at room temperature for a fixed duration as long as 10 s. The CVS effects on the capacitance-voltage curve-shift, the time-dependent leakage current and the time-dependent dielectric breakdown were measured and analyzed. CVS is observed to induce charge in Parylene-C and its interfaces with gold and Pentacene. The net induced charge is positive and negative for, respectively, negative and positive gate bias polarity during CVS. The magnitude of the charge accumulated following positive gate CVS is significantly higher than that following negative gate bias CVS in the range of 4 to 25 nC cm−2. In contrast, the leakage current during the negative gate stress is three orders of magnitude higher than that during the positive gate stress for the same bias stress magnitude. The charge buildup and leakage current are due to the trapping of electrons and holes near the Parylene-C/Pentacene interface as well as in the Parylene-C layer.Before the application of the CVS, a dielectric breakdown occurs at an electric field of 1.62 MV cm−1. After the application of the CVS, the breakdown voltage decreases and the density of the trapped charges increases as the stress voltage increases in magnitude, with the polarity of the trapped charges opposite to that of the stress voltage. The magnitude and direction of the capacitance-voltage curve-shift depend on the trapping and recombination of electrons and holes in the Parylene-C layer and in the proximity of the Parylene-C/Pentacene interface during CVS.

Analysis of threshold voltage instabilities in semi-vertical GaN-on-Si FETs

We present a first study of threshold voltage instabilities of semi-vertical GaN-on-Si trench-MOSFETs, based on double pulsed, threshold voltage transient, and UV-assisted C–V analysis. Under positive gate stress, small negative V th shifts (low stress) and a positive V th shifts (high stress) are observed, ascribed to trapping within the insulator and at the metal/insulator interface. Trapping effects are eliminated through exposure to UV light; wavelength-dependent analysis extracts the threshold de-trapping energy ≈2.95 eV. UV-assisted CV measurements describe the distribution of states at the GaN/Al2O3 interface. The described methodology provides an understanding and assessment of trapping mechanisms in vertical GaN transistors.

An Investigation of Frequency Dependent Reliability and Failure Mechanism of pGaN Gated GaN HEMTs

This paper presents a frequency dependent reliability study of commercially available GaN HEMTs. Both circuit and device-level experiments were performed to better understand the device-level cause of degradation. It was determined through step-frequency analysis performed in a boost converter that there is a frequency-dependent device degradation for positive gate stress. The point of degradation and its primary effect on the converter before the circuit ultimately failed have been analyzed with converter efficiency, gate current, and gate voltage overshoot. The findings of this experiment clearly show a decline in efficiency and voltage overshoot and increment in gate current, which are linked to device degradation. Furthermore, the recovery behavior of degraded devices has been investigated. However, after initial degradation, devices did not show any signs of recovery over twenty-four-hour recovery periods. The causal origin of these phenomena associated with the gate structure of the device was established by gate step-stress testing as well as an examination and analysis of the possible conduction mechanisms through the gate structure.

Positive temperature dependence of time-dependent breakdown of GaN-on-Si E-mode HEMTs under positive gate stress

We report an extensive analysis of the time-dependent breakdown of E-mode GaN-on-Si power HEMTs subjected to positive gate stress and demonstrate that TTF (time-to-failure) has a positive temperature dependence. The analyzed devices have a p-type gate; large (60 A) power transistors were subjected to positive stress at different voltages and temperatures ranging from 25 °C to 250 °C. The original results collected in this paper demonstrate that (i) constant voltage stress induces a gradual decrease in gate leakage current, which is ascribed to hole-trapping in Mg-acceptors located at the p-GaN/AlGaN interface; (ii) this trapping process becomes less pronounced at high temperatures, due to a faster detrapping from the shallow Mg-related traps; (iii) the devices stressed at the same voltage and different temperatures show a similar initial gate leakage, due to the fact that in the analyzed regime, gate conduction is dominated by Fowler-Nordheim tunneling, a field-related, rather than thermally activated, process; (iv) the time-to-failure has a positive temperature dependence. The latter result is explained by considering that time-dependent breakdown occurs due to the accumulation of positive charges at the p-GaN/AlGaN interface, which results in an increased injection of 2DEG electrons into the p-GaN layer, where they are accelerated by the electric field. High temperatures favor the detrapping of holes, thus reducing this process and leading to a better stability.

Effect of border traps on the threshold voltage instability of fluoride-doped AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors

In this paper, we performed a systematic investigation of the threshold-voltage (Vth) instability of enhancement-mode (E-mode) AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs). The E-mode MIS-HEMTs are firstly demonstrated by using the fluoride plasma treatment and the Vth is characterized by 1.55 V after the 400 °C post-metallization annealing (PMA). This PMA which is used to eliminate the interface trap induced by the plasma damage exhibits a trade-off between the negative shift of Vth and the performance improvement both for the ON- and OFF-states. Nevertheless, a significant hysteresis occurs even after employing the PMA indicating that either interface traps or border traps in the insulator tend to capture the electrons, wherefore the traps result in a negative net charge. According to this result, both pulsed measurement and stress measurement with DC measurement are implemented to identify the property of the trap state. A significantly positive Vth shift is observed both in a long pulsed-width measurement and DC measurement right after the positive gate stress which implies that border traps with a long emission time constant induce a retentive Vth even under the DC measurement. Besides, compared to the fluoride-doped HEMT (i.e. HEMT without insulator insertion), fluoride-doped MIS-HEMT exhibiting a more significant Vth shift suggest that additional border traps are created through the fluoride ion diffusion during the high temperature annealing.

Recovery behaviors in n-channel LTPS-TFTs under DC stress

In this paper, the degradation and recovery behaviors of polycrystalline silicon (poly-Si) thin film transistor (TFT) under direct current (dc) stress were investigated. Under positive or negative gate stress with a drain bias stress, the similar degradation and recovery behaviors were observed. The similar recovery is a limited one compared to the degradation before removing the bias stress. It is determined that hot-carrier effect is the key degradation mechanism under the positive or negative gate stress condition. The devices without drain bias stress appear no recovery behavior after removing the stress, which implies that the hot-carrier degradation is mainly because of the lateral electrical field rather than the vertical electrical field. In contrast to the degradation caused by hot-carrier effect, the degradation caused by the vertical gate electrical field cannot be recovered after removing the stress.

Time-Dependent Dielectric Breakdown in High-Voltage GaN MIS-HEMTs: The Role of Temperature

We have investigated time-dependent dielectric breakdown in high-voltage AlGaN/GaN metal–insulator–semiconductor high-electron mobility transistors, with a focus specifically on the role of temperature under positive gate stress conditions. We aim toward understanding the temperature dependence of progressive breakdown (PBD) as well as hard breakdown. We find that the temperature dependence of time-to-first breakdown, hard breakdown, and the gate current evolution during PBD all share similar, shallow activation energies that suggest a common underlying mechanism. However, the gate current noise during PBD seems to be independent of temperature and is likely due to a tunneling process. Understanding of temperature-dependent breakdown is essential to developing accurate device lifetime estimates.

Investigation of &lt;italic&gt;In Situ&lt;/italic&gt; SiN as Gate Dielectric and Surface Passivation for GaN MISHEMTs

In this paper, we present a systematic investigation of metal–organic chemical vapor deposition-grown in situ SiN as the gate dielectric and surface passivation for AlGaN/GaN metal insulator semiconductor high electron mobility transistors (MISHEMTs). The dielectric constant and breakdown field of the in situ SiN were extracted from devices with varied gate dielectric thicknesses. Using frequency-dependent capacitance–voltage and parallel conductance methods, we obtained a low trap density of $\sim 3\times 10^{12}$ cm $^{-2}$ eV $^{-1}$ at the SiN/AlGaN interface. The MISHEMTs with a source–drain distance of $3~\mu \text{m}$ show a maximum drain current of 1560 mA/mm and a high on/off current ratio of $10^{9}$ . The device threshold voltage ( ${V}_\textsf {th}$ ) stability was assessed by means of both negative and positive gate stress measurements, as well as temperature-dependent $ {I}_\textsf {D}$ – ${V}_\textsf{G}$ measurements. We observed a minimal $ {V}_\textsf{th}$ shift of ~0.4 V under both 3000 s gate stress of ${V}_\textsf {GS}= 4$ V and up to 200 °C thermal stimulation. Furthermore, combining the in situ SiN with plasma-enhanced chemical vapor deposition SiN, we developed a bilayer passivation scheme for effective suppression of current collapse. Employing the high-quality in situ SiN, we have demonstrated large-area GaN MISHEMTs on Si with a gate width of 20 mm, showing a low off-state leakage of $2~\mu \text{A}$ /mm at 600 V and a low dynamic/static ON-resistance ratio. The device results show great advantages of employing in situ SiN in D-mode GaN MISHEMTs for high-efficiency power switching applications.

Technology and Reliability of Normally-Off GaN HEMTs with p-Type Gate

GaN-based transistors with p-GaN gate are commonly accepted as promising devices for application in power converters, thanks to the positive and stable threshold voltage, the low on-resistance and the high breakdown field. This paper reviews the most recent results on the technology and reliability of these devices by presenting original data. The first part of the paper describes the technological issues related to the development of a p-GaN gate, and the most promising solutions for minimizing the gate leakage current. In the second part of the paper, we describe the most relevant mechanisms that limit the dynamic performance and the reliability of GaN-based normally-off transistors. More specifically, we discuss the following aspects: (i) the trapping effects specific for the p-GaN gate; (ii) the time-dependent breakdown of the p-GaN gate during positive gate stress and the related physics of failure; (iii) the stability of the electrical parameters during operation at high drain voltages. The results presented within this paper provide information on the current status of the performance and reliability of GaN-based E-mode transistors, and on the related technological issues.

Impact of work function of the silicon bottom-gates on electrical instability in InGaZnO thin film transistors

The electrical instability in amorphous InGaZnO (IGZO) thin film transistors has been investigated for different doping types and concentrations of silicon bottom-gates. The gate current (IG) was measured to prove that the threshold voltage shifts (∆VTH) were due to electron and hole trapped charges under positive and negative gate stress, respectively. After the gate stress, the ∆VTH in IGZO transistors depend on the work function of the silicon gates. The ∆VTH listed in order of magnitude are ∆VTH-n+-gate>∆VTH-n-gate>∆VTH-p-gate>∆VTH-p+-gate after a positive gate stress and a positive thermal illumination stress, but this is reversed after a negative gate stress and a negative thermal illumination stress. The more significant ∆VTH after a negative thermal illumination stress than after positive thermal illumination stress may be attributed to the low-level injection under light illumination. To minimize ∆VTH in IGZO transistor with a silicon bottom-gate, a low-doped gate is recommended.

Effect of Gate Voltage Stress on InGaAs MOSFET With HfO2or Al2O3Dielectric

InGaAs nMOSFETs with Al2O3 and HfO2 as dielectric are analyzed. The devices with Al 2O3 show a slightly better subthreshold slope. Both high- $\kappa$ 's have an equal transconductance frequency dispersion $(g_{m}\mbox{-}f)$ . A reduction of $g_{m}\mbox{-}f$ is reached by scaling the HfO2 thickness. Positive gate stress leads to an increase in threshold voltage and subthreshold slope for all oxides. DC- $g_{\max}$ degradation is related purely to creation or activation of additional border traps during stress. The RF- $g_{\max}$ is not degraded. Similar time constants hint to a relation between the (semi-)stable degradation of DC- $g_{\max}$ and the threshold voltage increase. For the samples with HfO2, the effects of gate-stress induced additional border traps can only be detected at low frequencies. The created or activated defects are most likely located deep in the oxide. For Al2O3, the effect of additional border traps is also measurable at higher frequencies. The defects are created both closer to the Al2O3/InGaAs interface and deeper in the oxide.