Positive Gate Bias Stress Research Articles

Charging Effect by Fluorine-Treatment and Recess Gate for Enhancement-Mode on AlGaN/GaN High Electron Mobility Transistors.

An enhancement-mode AlGaN/GaN metal-insulator-semiconductor high-electron- mobility-transistor was fabricated using a recess gate and CF4 plasma treatment to investigate its reliable applicability to high-power devices and circuits. The fluorinated-gate device showed hysteresis during the DC current-voltage measurement, and the polarity and magnitude of hysteresis depend on the drain voltage. The hysteresis phenomenon is due to the electron trapping at the Al2O3/AlGaN interface and charging times longer than milliseconds were obtained by pulse I-V measurement. In addition, the subthreshold slope of the fluorinated-gate device was increased after the positive gate bias stress because of the two-dimensional electron gas reduction by ionized fluorine. Our systematic observation revealed that the effect of fluorine ions should be considered for the design of AlGaN/GaN power circuits.

Long-Term Aging of Al2O3 Passivated and Unpassivated Flexible a-IGZO TFTs

Amongst the new materials studied for the fabrication of high-performance flexible thin-film transistors (TFTs), amorphous indium-gallium-zinc-oxide (a-IGZO) exhibits a combination of advantages that enables its application in commercial electronics. Hence, it is crucial to understand the electrical stability of a-IGZO TFTs over long periods of time. In this work, we present the effects of long-term aging on Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> passivated and unpassivated flexible a-IGZO TFTs over a period of 80 months (≈ 6.5 years). It is found that although remaining functional, these devices are influenced by different instability effects. More specifically, positive gate bias stress experiments indicate that the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> passivation layer contributes to the degradation of the devices' performance. These results show that the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> passivation, although beneficial to the initial device stability, does not prevent the degradation of the passivated devices in comparison with their unpassivated counterparts after long periods of storage.

Abnormal double-hump phenomenon in amorphous In-Ga-Zn-O thin-film transistor under positive gate bias temperature stress

This paper presents an investigation of the abnormal hump phenomenon in amorphous indium gallium zinc oxide thin-film transistors under positive gate bias and temperature stress (PBTS). During PBTS, the current-voltage curve shows a severe hump and an abnormal double hump. Additional stress tests were conducted under long-term and low-temperature PBTS and current stress (CS), then the capacitance-voltage (C-V) curves after PBTS and CS were compared to identify the causes of the double-hump phenomenon. Threshold voltages VT were extracted at two levels of normalized drain current IDS: high VT_H at IDS = 10-8 A and low VT_L at IDS = 10-12 A. After 10,000 s, high-temperature PBTS shifted VT_H by + 3.48 V and VT_L by –3.20 V; low-temperature PBTS shifted VT_H by + 1.46 V and VT_L by –0.56 V; and CS shifted VT_H by + 5.02 V and VT_L by –0.98 V. Saturation measurement indicated that degradation of the source region has the strongest influence on degradation of IDS-VGS during CS; these results indicate trapping of charged species. In addition, both high-temperature PBTS and CS affected the C-V results; these changes indicate creation of defect states. Therefore, we hypothesize that the severe hump occurred because of a combination of trapping of charged species and creation of defect states. The double hump occurred only during PBTS. Thus, we hypothesize that the double hump was caused by trapping of ionized oxygen vacancies in the back channel. In a 2D TCAD simulation, the proposed hypothesis suggests that the migration of defect states and charged species affect the hump phenomenon. By changing distribution of shallow donor-like states in the channel and by changing the number of trapped electrons, we obtained simulated curves that were well fitted to our experimental results.

Oxygen Radical Control via Atmospheric Pressure Plasma Treatment for Highly Stable IGZO Thin-Film Transistors

In this article, the atmospheric pressure plasma (APP) treatment method is proposed to solve the instability problem under a long-term electrical bias stress through the semiconductor surface treatment without degrading the excellent electrical characteristics of oxide thin-film transistors (TFTs). The high-energy oxygen radicals produced by the APP without a vacuum system affect the electrical properties by quickly and easily changing the chemical state of the oxygen-related bonds in the semiconductor. Consequently, the amorphous indium gallium zinc oxide TFTs with suitable APP treatment showed excellent bias stress stability and electrical characteristics in comparison with the APP-untreated oxide TFTs. The threshold voltage shift after the negative gate bias stress and positive gate bias stress duration of 1 h significantly reduced from -9.9 to -0.7 V and from +6.7 to +0.5 V, respectively. In addition, the average field-effect mobility remarkably enhanced from 10.8 to 14.8 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs and the hysteresis behavior reduced from 0.31 to 0.12 V while maintaining the key parameters of TFTs such as subthreshold swing, ON/OFF ratio, and ${V}_{ \mathrm{\scriptscriptstyle ON}}$ .

Impacts of Ammonia Gas Plasma Surface Treatment on Polycrystalline-Silicon Junctionless Thin-Film Transistor

The impacts of ammonia gas (NH3) plasma treatment on the performance and positive gate bias stress (PGBS) of polycrystalline-silicon (poly-Si) junctionless thin-film transistor (JL-TFT) are studied. A −0.785-V threshold voltage ( $V_{\mathrm {TH}}$ ) shift of JL-TFT due to the NH3 plasma treatment is observed, which is attributed to the fixed oxide charge effect of the plasma-induced interfacial layer (PIL). In addition, the transconductance of JL-TFT with the NH3 plasma treatment is enhanced by ~2.73 times due to the trap state passivation of grain boundaries in the poly-Si, and the ON-state current ( $I_{\mathrm {ON}}$ ) is enhanced by ~2.91 times. In addition to the performance enhancement of JL-TFT by the plasma process, the $V_{\mathrm {TH}}$ shift of poly-Si JL-TFT under PGBS is suppressed from −0.240 to −0.063 V after the plasma treatment. It is attributed to the less degradation of insulator/channel interface due to the growth of PIL by the plasma process. Moreover, the $I_{\mathrm {ON}}$ degradation of JL-TFT after PGBS is also improved from −19% to −16% after the plasma treatment. As the carrier transport of JL-TFT is the bulk conduction rather than the surface conduction of conventional inversion-mode TFT, the degradation of insulator/channel interface would exhibit less impacts on the $I_{\mathrm {ON}}$ . The improvement of performance and PGBS of JL-TFT by the NH3 plasma treatment would be beneficial to the application of 3-D integrated circuits.

Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H-SiC MOSFET

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

Abnormal hysteresis formation in hump region after positive gate bias stress in low-temperature poly-silicon thin film transistors

Degradation in low-temperature polycrystalline-silicon thin-film transistors after electrical stress was thoroughly investigated in this work. Main channel degradation, abnormal hump generation and hysteresis appearing in the hump region can be observed after positive bias stress. Furthermore, the difference in subthreshold swing (SS) values between forward/reverse sweep is observed. The electron trapping into the gate insulator (GI) dominates the main degradation and the hump generation. Additionally, the difference in SS values which appears in the hump region is attributed to the interface traps and the hysteresis is caused by electron trapping/detrapping into GI.

Tunable Stability of All-Inkjet-Printed Double-Gate Carbon Nanotube Thin Film Transistors

In this letter, we improved the stability of all-inkjet-printed carbon nanotube thin film transistors (CNT TFTs) by employing a double gate (DG) structure under an optimal bias condition. In the single-gate structure, the positive threshold voltage ( $\text{V}_{\text {TH}}$ ) shift under 10 V positive gate bias stress (PGBS) was significantly reduced with poly(4-vinylphenol) passivation. However, after 100 s, the on-current level was decreased, and a large negative $\text{V}_{\text {TH}}$ shift was observed. We adopted DG CNT TFTs for a further improvement. When −3 V was applied to the top gate, the DG CNT TFTs not only exhibited a much lower $\text{V}_{\text {TH}}$ shift but also showed a stabilized on-current level. When an appropriate bias is applied to the top gate, charge trapping is induced at the top gate interface and it might balance between the positive and negative shifts. As a result, the overall stress effect is reduced. The p-type only inverter adopting a DG CNT TFT showed improved stability under −3 V of top gate bias. Our experimental result shows that DG structure is a promising candidate for various CNT circuit designs.

Mobility Improvement of Amorphous Indium-gallium-zinc Oxide Thin Film Transistor by Roll-to-roll Compatible Plasma Treatment

For the mobility enhancement of amorphous indium-gallium-zinc oxide thin film transistor (a-IGZO TFT), Ar plasma treatment was proposed at room temperature under air as an economic and continuous process. Through the suggested method, the field effect mobility (μFE) improves significantly from 1.69 cm²/V·s to 4.20 cm²/V·s. The increase of oxygen vacancy (VO) and decrease of metal-oxide bonding are observed in the plasma treated device by X-ray photoelectron spectroscopy (XPS) analysis. The increased VO is thought to enhance the carrier concentration and mobility. Some of VO, however, will be an inactive and deep state in the forbidden energy gap of IGZO and deteriorate the electrical stability. To avoid this side effect, the selective Ar plasma treatment was also adapted on source/drain (S/D) contact region and threshold voltage shift under the constant positive gate bias stress was measured to decrease from 6.2 V to 4.8 V, which is similar with the untreated device of 4.4 V. In the contract region plasma device, the μFE improves also by 39.6 % to 2.35 cm²/V·s mainly due to the reduction of S/D contact resistance extracted by the transmission line method (TLM).

Study of Positive-Gate-Bias-Induced Hump Phenomenon in Amorphous Indium–Gallium–Zinc Oxide Thin-Film Transistors

A positive-gate-bias stress (PBS)-induced hump phenomenon in staggered bottom-gate amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) is observed, and the possible reason is discussed. It is found that the hump phenomenon is closely related to device layouts. In conventional metal-over-active (MOA) structure, the hump current is independent of the channel width. However, for the active-over-metal (AOM) structure, the hump current disappears when the width of active layer exceeds a critical value. These results indicate that the hump current caused by PBS comes from parasitic edge transistors rather than back-channel transistors. Furthermore, the possible origin of channel edge conduction mechanism is checked by atomic force microscopy (AFM) and X-ray photoelectron spectroscopy (XPS) techniques. From AFM image, we notice that there is a long gentle slope at edge of active layer, which will enhance the electrical filed at local area and accelerate the device performance degradation under PBS condition. XPS measurements before and after PBS on devices at channel edge confirm our assumption, that is, the oxygen vacancy ( $\text{O}_{\mathrm {V}}$ ) content increases from 29.33% to 36.89% after PBS. This implies that the carrier concentration in channel edge is enhanced resulting in lower turn-on voltage of parasitic edge transistors, which, in turn, causes hump phenomenon.

Effects of hydrogen plasma treatment on the electrical performances and reliability of InGaZnO thin-film transistors

In this work, we have investigated the effects of hydrogen (H) plasma treatment on the electrical performances and reliability of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs). By optimizing the H plasma treatment time, the a-IGZO TFT with H plasma treatment time of 1 min exhibits excellent electrical performances and reliability, such as high field-effect mobility (μFE) of 26.5 cm2/V s and small threshold voltage shifts (ΔVth) value of 2.5 V and −2.3 V under positive gate bias stress (PBS) and negative gate bias stress (NBS) measurements without any passivation layers. The increased performance relies that the H plasma treatment not only could increase the carrier concentration (Ne) but also reduce the surface defects of channel layer and interface trap density of a-IGZO TFTs. The X-ray photo-electron spectroscopy measurement reveals that the H treatment passivated the oxygen vacancy (VO) defects and formed center-bonded complex states (HO or VO-H) in the a-IGZO films, which act as a shallow donor in a-IGZO films. Therefore, the high performances and excellent reliability of a-IGZO TFTs is suggesting that H is a very promising treatment for TFTs to be used for flexible thin film electronic applications.

Rare Metal‐Free High‐Performance Zinc–Tin Oxide Thin Film Transistors Using Efficient Energy Conversion of Microwave Annealing

Herein, a rare metal‐free oxide‐based semiconductor channel layer is constructed with excellent electrical properties and stabilities by fabricating zinc–tin oxide (ZTO) thin film transistors (TFTs) using tin (Sn) as the dopant element in ZnO. Furthermore, to improve the performance and stability of ZTO TFTs, microwave annealing (MWA) powered by energy conversion from electromagnetic energy to heat energy rather than heat transfer is conducted as the post‐deposition annealing (PDA) process of the ZTO channel layer. As a result, the electrical performance of ZTO TFTs is improved by MWA despite the much shorter PDA time because of the efficient energy transfer compared with that of furnace‐used thermal annealing (FTA) in conventional furnaces. The ZTO TFTs subjected to MWA exhibit a high on/off current ratio of 1.7 × 107, a high field‐effect mobility of 20.6 cm2 V−1 s−1, a small hysteresis voltage of 0.9 V, and a low interface trap density of 1.8 × 1012 cm−2 eV−1. In addition, the instabilities due to the positive and negative gate bias stresses at various operating temperatures are evaluated, and the results show that the instability of the ZTO TFT is significantly reduced by MWA.

Severe hump phenomenon induced by increased charge trapping and suppression of electron capture effect in amorphous In-Ga-Zn-O thin-film transistors under unipolar pulsed drain bias with static positive gate bias stress

This paper demonstrates degradation of amorphous indium gallium zinc oxide thin-film transistors under AC current stress (ACS), which is unipolar AC drain bias applied with positive static gate-bias stress. Under ACS, a severe hump occurs in current-voltage curves; the phenomenon causes a large negative shift similar to degradation caused by positive gate-bias stress (PGS) and a large positive shift by DC-current stress (DCS). In a saturation measurement, the degradation caused by factors in source region had the greatest effect on the hump phenomenon; this result confirms that hump characteristics are caused by charge trapping rather than by defect-state generation by impact ionization. The changes of threshold voltage shifts were extracted at two current levels, then analyzed by comparing with the results of PGS, DCS, and synchronized AC gate and drain bias stress. Positive shift in high-current level was larger after ACS (+3.80 V) than after PGS (+3.48 V) because current-caused Joule-heat thermally energized additional electrons to be trapped in front channel region. Negative shift in low-current level was larger after ACS (−2.42 V) than after DCS (−1.32 V). Under DCS, the amount of positively-charged species decreased because of neutralization of oxygen vacancies. The flow of current supports electron to be captured in ionized oxygen vacancies and the amount of negative shift is saturated at specific value (−1.32 V) under DCS. The characteristic time constant of stretched exponential curve-fitting reveals clear saturation tendency.

Verification of microwave annealing ambient effect on sol-gel-processed amorphous In–Ga–Zn–O thin-film transistors and application to inverter circuit

In this study, we conducted microwave annealing (MWA) on amorphous In–Ga–Zn–O (a-IGZO) thin films deposited by the sol-gel method, and then investigated the effects of ambient conditions on the electrical properties and reliability of a-IGZO thin-film transistors (TFTs) and on the optical and chemical properties of a-IGZO thin films. On the other hand, pure N2 ambient-treated TFTs exhibited the poorest transfer and output characteristics, but improved with increasing O2 mixing ratio. In terms of stability, pure O2 ambient-treated a-IGZO TFTs were excellent for both positive and negative gate bias stresses, but deteriorated with increasing N2 mixing ratio. Also, static and dynamic tests of resistor-loaded inverters were carried out. As a result, the pure O2 ambient-treated inverter showed excellent characteristics, while the pure N2 ambient-treated inverter had poor characteristics. Meanwhile, pure O2 ambient MWA has excellent carbon removal ability in sol-gel-processed a-IGZO films, lowering oxygen vacancies and impurities. Besides, it has an effect of increasing energy band gap, improving transmittance, increasing Fermi level and electron concentration, and contributing to improvement of mobility. Therefore, it was verified that MWA in pure O2 ambient is very beneficial to improve the optical and chemical properties of the sol-gel-processed a-IGZO thin film and the electrical properties of TFTs.

The influence of ZnO layer thickness on the performance and electrical bias stress instability in ZnO thin film transistors

Thin Film Transistors (TFTs) are the active elements for future large area electronic applications, in which low cost, low temperature processes and optical transparency are required. Zinc oxide (ZnO) thin film transistors (TFTs) on SiO2/n+-Si substrate are fabricated with the channel thicknesses ranging from 20 nm to 60 nm. It is found that both the performance and gate bias stress related instabilities of the ZnO TFTs fabricated were influenced by the thickness of ZnO active channel layer. The effective mobility was found to improve with increasing ZnO thickness by up to an order in magnitude within the thickness range investigated (20–60 nm). However, thinner films were found to exhibit greater stability in threshold voltage and turn-on voltage shifts with respect to both positive and negative gate bias stress. It was also observed that both the turn on voltage (Von) and the threshold voltage (VT) decrease with increasing channel thickness. Moreover, the variations in subthreshold slope (S) with ZnO thickness as well as variations in VT and Von suggest a possible dependence of trap states in the ZnO on the ZnO thickness. This is further correlated by the dependence of VT and Von instabilities with gate bias stress.

Electrical characteristics of amorphous indium‐tin‐gallium‐zinc‐oxide TFTs under positive gate bias stress

In this Letter, the authors investigate the electrical characteristics of amorphous indium-tin-gallium-zinc-oxide (a-ITGZO) thin-film transistors (TFTs) under positive gate bias stress (PBS). An as-prepared a-ITGZO TFT exhibits a mobility of 26.05 cm2/V⋅s, subthreshold swing of 183 mV, threshold voltage of −0.33 V, and on/off ratio of 1.34 × 108. These electrical characteristics deteriorate upon the application of PBS. The proposed experiments and simulations reveal that this deterioration can be attributed to the increase in the density of acceptor-like conduction band-tail states and donor-like Gaussian states within the bandgap of the a-ITGZO channel material.

Positive Bias Stress Instability of InGaZnO TFTs With Self-Aligned Top-Gate Structure in the Threshold-Voltage Compensated Pixel

The instability induced under positive gate-bias stress (PBS) in amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with self-aligned top-gate coplanar structure is investigated under the threshold-voltage $({V}_{T})$ compensated pixel scheme in the backplane of organic light-emitting diode displays and compared with that under a constant-PBS scheme . Based on the investigation, which combines the extraction of density of states, the decomposition of ${V}_{T}$ shift ( $\Delta {V}_{T}$ ), and technology computer-aided design, the unreleased electric field across the gate insulator (GI) and the maintained electron concentration are observed under the ${V}_{T}$ -compensated PBS condition. Indeed, the main difference between the two schemes originates from increasingly activated electron trapping within the GI deep-level traps and from the excessive oxygen-related peroxide bond-breaking in the a-IGZO-active film, i.e., O22− + $2 {e}^{-} \to$ O2− + O2−. Although the latter is quantitatively much smaller than the former, the two mechanisms are closely related to each other and should be jointly optimized. This is because a large amount of oxygen interstitials can generate a high density of GI electron traps. Since the GI deep-level trapping results in noticeable $\Delta {V}_{T}$ with an increase in PBS time, our results suggest that the $\Delta {V}_{T}$ should be seriously underestimated with respect to either the estimation of pixel lifetime or the assessment of ${V}_{T}$ -compensated pixel-circuit schemes, if the reliability/acceleration test relies only on the constant-PBS-based single-TFT device test.

Effect of Ambient Atmosphere on Abnormal Degradation Behavior in Metal-Oxide Thin-Film Transistor under Positive Gate-Bias and Temperature Stress

Effect of Ambient Atmosphere on Abnormal Degradation Behavior in Metal-Oxide Thin-Film Transistor under Positive Gate-Bias and Temperature Stress

Effect of Ambient Atmosphere on Abnormal Degradation Behavior in Metal-Oxide Thin-Film Transistor under Positive Gate-Bias and Temperature Stress

Proceedings of the International Display Workshops Volume 26 (IDW '19),Effect of Ambient Atmosphere on Abnormal Degradation Behavior in Metal-Oxide Thin-Film Transistor under Positive Gate-Bias and Temperature Stress

An Ultra‐Flexible Solution‐Processed Metal‐Oxide/Carbon Nanotube Complementary Circuit Amplifier with Highly Reliable Electrical and Mechanical Stability

AbstractHere, high‐performance flexible complementary metal‐oxide–semiconductor (CMOS) amplifiers with extremely stable electro‐mechanical characteristics by employing low‐temperature solution‐processed amorphous indium–gallium–zinc oxide (a‐IGZO) and single‐walled carbon nanotube (SWCNT) thin film transistors (TFTs) is demonstrated. The photochemical‐activated combustion sol–gel a‐IGZO and SWCNT TFTs show average saturation mobility of 6.82 and 0.51 cm2 V−1 s−1, respectively. Based on the devices, a‐IGZO/SWCNT‐based CMOS amplifiers are implemented on ultrathin and flexible substrates (thickness of ≈3 µm), exhibiting small‐signal gain and unity‐gain bandwidth of up to 25 dB and 25 kHz, respectively, with highly reliable characteristics from 1000 bending stress (radius of 125 µm) and positive gate bias stress conditions (for up to 3 h). The underlying mechanisms of the CMOS performance combined with large output impedance of the SWCNT load are investigated in detail via various circuit implementations and automatic integrated circuit modeling Spice simulation and comprehensive electrical analysis. To ensure the viability of the extremely stable electromechanical properties of the flexible amplifier, a numerical analysis is carried out based on finite‐element methods with an integrated circuit emphasis to find the best match of the CMOS architecture and optimized structural integrity, verifying highly reliable and scalable skin‐like electronics.