Abnormal double-hump phenomenon in amorphous In-Ga-Zn-O thin-film transistor under positive gate bias temperature stress

Abstract

This paper presents an investigation of the abnormal hump phenomenon in amorphous indium gallium zinc oxide thin-film transistors under positive gate bias and temperature stress (PBTS). During PBTS, the current-voltage curve shows a severe hump and an abnormal double hump. Additional stress tests were conducted under long-term and low-temperature PBTS and current stress (CS), then the capacitance-voltage (C-V) curves after PBTS and CS were compared to identify the causes of the double-hump phenomenon. Threshold voltages VT were extracted at two levels of normalized drain current IDS: high VT_H at IDS = 10-8 A and low VT_L at IDS = 10-12 A. After 10,000 s, high-temperature PBTS shifted VT_H by + 3.48 V and VT_L by –3.20 V; low-temperature PBTS shifted VT_H by + 1.46 V and VT_L by –0.56 V; and CS shifted VT_H by + 5.02 V and VT_L by –0.98 V. Saturation measurement indicated that degradation of the source region has the strongest influence on degradation of IDS-VGS during CS; these results indicate trapping of charged species. In addition, both high-temperature PBTS and CS affected the C-V results; these changes indicate creation of defect states. Therefore, we hypothesize that the severe hump occurred because of a combination of trapping of charged species and creation of defect states. The double hump occurred only during PBTS. Thus, we hypothesize that the double hump was caused by trapping of ionized oxygen vacancies in the back channel. In a 2D TCAD simulation, the proposed hypothesis suggests that the migration of defect states and charged species affect the hump phenomenon. By changing distribution of shallow donor-like states in the channel and by changing the number of trapped electrons, we obtained simulated curves that were well fitted to our experimental results.