The influence of ZnO layer thickness on the performance and electrical bias stress instability in ZnO thin film transistors

Divine Khan Ngwashi,Thomas Attia Mih,Richard B M Cross

doi:10.1088/2053-1591/ab6eee

Divine Khan Ngwashi, Thomas Attia Mih + Show 1 more

Open Access

https://doi.org/10.1088/2053-1591/ab6eee

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Abstract

Thin Film Transistors (TFTs) are the active elements for future large area electronic applications, in which low cost, low temperature processes and optical transparency are required. Zinc oxide (ZnO) thin film transistors (TFTs) on SiO2/n+-Si substrate are fabricated with the channel thicknesses ranging from 20 nm to 60 nm. It is found that both the performance and gate bias stress related instabilities of the ZnO TFTs fabricated were influenced by the thickness of ZnO active channel layer. The effective mobility was found to improve with increasing ZnO thickness by up to an order in magnitude within the thickness range investigated (20–60 nm). However, thinner films were found to exhibit greater stability in threshold voltage and turn-on voltage shifts with respect to both positive and negative gate bias stress. It was also observed that both the turn on voltage (Von) and the threshold voltage (VT) decrease with increasing channel thickness. Moreover, the variations in subthreshold slope (S) with ZnO thickness as well as variations in VT and Von suggest a possible dependence of trap states in the ZnO on the ZnO thickness. This is further correlated by the dependence of VT and Von instabilities with gate bias stress.

Highlights

Thin Film Transistors (TFTs) are the active elements for future large area electronic applications, in which low cost, low temperature processes and optical transparency are required
Poly-silicon thin film transistors (TFTs) have so far been the main attractive alternative to amorphous silicon TFTs used in large area electronic applications such as in flat panel displays [1, 2]
Zinc oxide (ZnO) TFTs fabricated using the sputtered ZnO layers produced in this work exhibited the following characteristics

Summary

INTRODUCTION

Poly-silicon thin film transistors (TFTs) have so far been the main attractive alternative to amorphous silicon TFTs used in large area electronic applications such as in flat panel displays [1, 2]. A first order approximation of Rsp is often given by the analytical expression (1); where W is the channel width, ρ the source-drain resistivity, the junction depth, the channel thickness and ξ is a us scaling factor [11, 12]. In physical terms this means that both the doping concentration and the channel thickness can be used to modulate Rsp and the device performance. The purpose of this work is to demonstrate that both performance and gate bias stress related electrical instability in ZnO TFTs can be modulated via thickness optimisation of the ZnO active layer

EXPERIMENTAL

AND DISCUSSION

CONCLUSION