Significant Bit Research Articles

Digital Watermarking Implementation Of Digital Watermarking On Images Using The Least Significant Bit Method

The ease of accessing the internet in this modern era has led to illegal crimes, especially data copying, data distribution and abuse of intellectual property rights. From these problems emerged a method of securing data and information, namely watermark. Watermark is used for data security techniques, both for copyright protection and digital signatures in the visible and invisible realms. One of the data security techniques used here is to use the least significant bit (LSB) method. This method is used for data security or images that contain watermarks, for example on currency there is usually a logo to distinguish real and fake currencies. This study uses nine host images taken from the https://www.kaggle.com/datasets/felicepollano/watermarked-not-watermarked-images dataset with different sizes, namely 513 x 513 pixels, 488 x 350 pixels, 467 x 350 pixels, 500 x 333 pixels, 512 x 301 pixels, 490 x 350 pixels, 500 x 332 pixels, 400 x 266 pixels, and 500 x 308 pixels. As for the label image, it uses the uty logo which has a size of 50 x 50 pixels, 80 x 80 pixels, and 124 x 124 pixels. From the results of the watermark test that has been carried out using the LSB method, the average PNSR value is 65 dB, so it can be concluded that the watermark research using the LSB method gets pretty good image results and can be used for data security.
 Keywords: Watermark, Least Significant Bit, Peak Signal to Noise Ratio (PNSR)

Data Security Using Color Image Based on Beaufort Cipher, Column Transposition and Least Significant Bit (LSB)

One of cryptography algorithm which used is beaufort cipher. Beaufort cipher has simple encryption procedure, but this algorithm has good enough endurance to attack. Unauthorized people cannot break up decrypt without know matrix key used. This algorithm used to encrypt data in the form of text called plaintext. The result of this algorithm is string called ciphertext which difficult to understood that can causing suspicious by other people. Beaufort cipher encryption tested with avalanche effect algorithm with modified one, two, three and all key matrix which resulting maximum 31.25% with all key modification so another algorithm is needed to get more secure. Least Significant Bit (LSB) used to insert ciphertext created to form of image. LSB chosen because easy to use and simple, just alter one of last bit image with bit from message. LSB tested with RGB, CMYK, CMY and YUV color modes inserted 6142 characters resulting highest PSNR value 51.2546 on YUV color mode. Applying steganography technique has much advantage in imperceptibility, for example the image product very similar with original cover image so the difference can not differentiate image with human eye vision. Image that tested as much ten images, that consist of five 512 x 512 and five 16 x 16 image. While string message that used is 240, 480 and 960 character to test 512 x 512 image and 24, 48 and 88 character to test 16 x 16 image. The result of experiment measured with Mean Square Error (MSE) and Peak Signal Ratio (PSNR) which has minimum PSNR 51.2907 dB it means stego image that produced hood enough. Computation time calculation using tic toc in matlab resulting fastest value 0.041636 to encrypt 2000 character and the longest time is 4.10699 second to encrypt 6000 character and inserting to image. Amount of character and amount of multi algorithm can affecting computation time calculation.

FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis.

Artificial intelligence (AI) has revolutionized present-day life through automation and independent decision-making capabilities. For AI hardware implementations, the 6T-SRAM cell is a suitable candidate due to its performance edge over its counterparts. However, modern AI hardware such as neural networks (NNs) access off-chip data quite often, degrading the overall system performance. Compute-in-memory (CIM) reduces off-chip data access transactions. One CIM approach is based on the mixed-signal domain, but it suffers from limited bit precision and signal margin issues. An alternate emerging approach uses the all-digital signal domain that provides better signal margins and bit precision; however, it will be at the expense of hardware overhead. We have analyzed digital signal domain CIM silicon-verified 6T-SRAM CIM solutions, after classifying them as SRAM-based accelerators, i.e., near-memory computing (NMC), and custom SRAM-based CIM, i.e., in-memory-computing (IMC). We have focused on multiply and accumulate (MAC) as the most frequent operation in convolution neural networks (CNNs) and compared state-of-the-art implementations. Neural networks with low weight precision, i.e., <12b, show lower accuracy but higher power efficiency. An input precision of 8b achieves implementation requirements. The maximum performance reported is 7.49 TOPS at 330 MHz, while custom SRAM-based performance has shown a maximum of 5.6 GOPS at 100 MHz. The second part of this article analyzes the FinFET 6T-SRAM as one of the critical components in determining overall performance of an AI computing system. We have investigated the FinFET 6T-SRAM cell performance and limitations as dictated by the FinFET technology-specific parameters, such as sizing, threshold voltage (Vth), supply voltage (VDD), and process and environmental variations. The HD FinFET 6T-SRAM cell shows 32% lower read access time and 1.09 times better leakage power as compared with the HC cell configuration. The minimum achievable supply voltage is 600 mV without utilization of any read- or write-assist scheme for all cell configurations, while temperature variations show noise margin deviation of up to 22% of the nominal values.

Generalized implicit-key attacks on RSA

RSA (Rivest–Shamir–Adleman) is a fundamental algorithm in information security for public key cryptography. Recently, a novel attack scenario of RSA with two implicitly correlated private keys, i.e., implicit-key attack was formulated. The lattice-based cryptanalytic strategy was proposed to factor RSA moduli using given implicit hints referring to known quantities of unknown common bits distributed among unknown private keys. In this paper, we review the simple basic scenario in which two RSA instances share known amounts of MSBs (most significant bits) and LSBs (least significant bits). We extend it to a more complex situation, where the amounts of MSBs and LSBs shared along with a few common blocks of middle bits are known. In addition, based on the above theoretical analyses, we present a generalized implicit-key attack framework. Our results disclose the vulnerability of RSA using correlated private keys with implicit information. Furthermore, numerical computer experiments are conducted to assess the validity of basic and extended implicit-key attacks.

Combinatorial MAB-Based Joint Channel and Spreading Factor Selection for LoRa Devices.

Long-Range (LoRa) devices have been deployed in many Internet of Things (IoT) applications due to their ability to communicate over long distances with low power consumption. The scalability and communication performance of the LoRa systems are highly dependent on the spreading factor (SF) and channel allocations. In particular, it is important to set the SF appropriately according to the distance between the LoRa device and the gateway since the signal reception sensitivity and bit rate depend on the used SF, which are in a trade-off relationship. In addition, considering the surge in the number of LoRa devices recently, the scalability of LoRa systems is also greatly affected by the channels that the LoRa devices use for communications. It was demonstrated that the lightweight decentralized learning-based joint channel and SF-selection methods can make appropriate decisions with low computational complexity and power consumption in our previous study. However, the effect of the location situation of the LoRa devices on the communication performance in a practical larger-scale LoRa system has not been studied. Hence, to clarify the effect of the location situation of the LoRa devices on the communication performance in LoRa systems, in this paper, we implemented and evaluated the learning-based joint channel and SF-selection methods in a practical LoRa system. In the learning-based methods, the channel and SF are decided only based on the ACKnowledge information. The learning methods evaluated in this paper were the Tug of War dynamics, Upper Confidence Bound 1, and ϵ-greedy algorithms. Moreover, to consider the relevance of the channel and SF, we propose a combinational multi-armed bandit-based joint channel and SF-selection method. Compared with the independent methods, the combinations of the channel and SF are set as arms. Conversely, the SF and channel are set as independent arms in the independent methods that are evaluated in our previous work. From the experimental results, we can see the following points. First, the combinatorial methods can achieve a higher frame success rate and fairness than the independent methods. In addition, the FSR can be improved by joint channel and SF selection compared to SF selection only. Moreover, the channel and SF selection dependents on the location situation to a great extent.

Steganography: Combination of Least Significant Bit (LSB) and Bit-Plane Complexity Segmentation (BPCS) Methods for Hiding Massage on Image and Audio

Steganography: Combination of Least Significant Bit (LSB) and Bit-Plane Complexity Segmentation (BPCS) Methods for Hiding Massage on Image and Audio

Design of Modified Booth’s Encoder Using SPST technique

This paper presents the design and implementation of signed-unsigned Modified Booth Encoding (SUMBE) multiplier. The present Modified Booth Encoding (MBE) multiplier and the Baugh-Wooley multiplier perform multiplication operation on signed numbers only. Therefore, this paper presents the design and implementation of SUMBE multiplier. The modified Booth Encoder circuit generates half the partial products in parallel. By extending sign bit of the operands and generating an additional partial product the SUMBE multiplier is obtained. The Carry Save Adder (CSA) tree and the final Carry Look ahead (CLA) adder used to speed up the multiplier operation. Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system. The proposed radix-2 modified Booth algorithm MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC.

A Data Weight Averaging-Inspired Digital Calibration Method for a 10-Bit Noise-Shaping Successive Approximation Register

This paper presents a digital calibration method for a 10-bit noise-shaping Successive Approximation Register Analog to Digital Converter (SAR ADC). The proposed calibration method is inspired by its Data Weight Averaging (DWA) counterpart, but stays static, while achieving a similar Integral Nonlinearity (INL) and 1.3 dB better Signal-to-Noise Ratio (SNR) in measurements without oversampling. This advantage in SNR holds until an Oversampling Ratio (OSR) of 2 for the proposed method, which also saves 50 % power. At a 1.2 V power supply, the ADC consumes a power of 70 µW at a conversion rate of 50 kHz. Fabricated using 55 nm Complementary Metal Oxide Semiconductor (CMOS) Metal-Oxide-Metal Capacitor (MOMCAP) technology, it occupies an active area of 370 µm × 350 µm, when achieving an INL of 0.3 Least Significant Bit (LSB) and an SNR of 66.9 dB at an OSR of 8.

A novel smooth PON evolution based on signal cancellation

A novel smooth evolution from current PONs to next generation PON is proposed. The new PON link is added into the deployed optical distribution network to reuse the existing infrastructure. Pre-cancellation is applied to eliminate the crosstalk from the new PON signal to the legacy PON signal. In the optical line terminator (OLT), the legacy PON signal is added with an inverse new PON signal before optical modulation. The optical signal from the legacy PON transmitter is the sum of the legacy PON signal and the inverse new PON signal. Such optical signal will be received together with new PON optical signal in the existing optical network units (ONUs). The added inverse new PON signal cancels the received new PON signal, with the legacy PON signal left. Compared with the previous coding based smooth evolution, the effective bit rate of the new PON signal is higher as the code efficiency is 100% and the operation complexity is lower as coding and decoding are not required. The signal cancellation based smooth evolution from 1.25 Gb/s, 2.5 Gb/s, and 10 Gb/s legacy PON to 10 Gb/s new generation PON is demonstrated. The tested results show the feasibility of the proposed smooth evolution.

A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces

This article presents a 25-Gb/s single-ended four-level pulse-amplitude modulation (PAM-4) receiver with a time-windowed least significant bit (LSB) decoder for high-speed memory interfaces. The proposed PAM-4 decoding technique obviates the need for additional comparators and reference voltages that are required in conventional PAM-4 decoders. Similar to conventional non-return-to-zero (NRZ) receivers, the proposed PAM-4 receiver uses only one comparator by decoding the LSB through time-windowing the outputs of the comparator that is used to decide a most significant bit (MSB). Therefore, the additional power overhead from a power-hungry analog front-end (AFE) and high-speed clock buffers is minimized in the proposed PAM-4 receiver because it is proportional to the number of comparators. Accordingly, the proposed PAM-4 receiver can achieve superior energy efficiency. Furthermore, the elimination of the use of reference voltages reduces the hardware cost and design complexity. A prototype single-ended PAM-4 receiver was fabricated in a 28-nm CMOS technology. It occupies 0.008 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> and consumes 0.34 pJ/bit at 25 Gb/s.

Probabilistic constellation shaping-aided underwater acoustic communication with vector approximate message passing iterative equalization.

A probabilistic constellation shaping (PCS)-aided single-carrier transceiver is proposed to improve spectral efficiency for underwater acoustic (UWA) communications. At the transmitter, the information bits are input into a distribution matcher followed by a systematic binary encoder, which yields a sequence of sign bits with a uniform distribution and a sequence of amplitude bits with a non-uniform distribution. Based on these two sequences, the PCS is then realized by mapping coded bits onto a quadrature amplitude modulation constellation. At the receiver, an improved frequency-domain turbo equalizer based on the vector approximate message passing (VAMP) is proposed for the PCS-UWA communication system to eliminate the multipath interference. It exploits the a priori symbol probability information benefiting from the PCS at the beginning of the turbo iteration and over the self-iteration of the VAMP soft equalizer, improving the symbol detection performance. Finally, the first experimental demonstration of a deep-sea PCS-UWA communication system and numerical simulation of shallower water are presented. The experimental results reveal the PCS-UWA communication system significantly outperforms traditional systems with no PCS. Also, the proposed receiver is superior to the classical adaptive turbo equalizer based on the improved proportionate normalized least mean square algorithm even with data reuse.

A Matching Strategy Based on Full-Permutation Bisection for Data Converters

This paper presents a top-to-bottom element-matching strategy based on a full-permutation bisection algorithm for data converters. By bisecting the composing elements and recombining them for a minimal weight difference, the linearity of the data converter can be significantly improved. Three different approaches have been implemented for the proposed algorithm, and they are based on linear programming, stochastic quantization, and maximal linearly independent subset (MLIS) respectively. Their pros and cons have been discussed and simulated exhaustively, and all of them have been silicon proved via capacitive digital to analog converters in 180-nm technology. Measurement results of twenty dies for each approach verified the aforementioned theoretical analysis, and all three approaches could achieve sub-30 ppm for all codes after calibration. The worst integral nonlinearity at the most significant bit after calibration can be improved from 402 ppm to 10.9 ppm, which is equivalent to a 5.2-bit boost, indicating a promising potential of the proposed matching strategy. Besides, the MLIS-based approach is the first optimal-combination-algorithm-based matching strategy that achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathcal{O}(N)$</tex-math> </inline-formula> time complexity, as the authors know.

Design of a high-accuracy time-to-digital converter based on dual-edge signals

Among numerous time-to-digital converters (TDC), tapped delay line (TDL) is the most commonly used architecture. However, its dead time of more than two cycles is inefficient for applications with high measurement rates. Limited by the device process, the delay of each cell in the TDL exhibits a random and uneven distribution, degrading the linearity of the TDC. In this study, a dual-edge TDL structure is proposed. By improving original pulse-holding circuit, the propagated signal injected into the fine measurement chain is alternately switched between rising and falling edge signals to decrease the dead time to one cycle. The nonlinearity problem is alleviated by an enhanced tapped sampling sequence circuit. A dual-edge “1” count encoder is introduced to effectively simplify the difficulty of addressing the bubble problem. Bit-by-bit calibration and a moving average filter are adopted to improve accuracy. The proposed scheme has been verified on a Xilinx Kintex-7 FPGA platform. The resolution (least significant bit, LSB1) is 12.07 ps when the propagated signal in the TDL is the rising edge. The differential nonlinearity (DNL) is [-0.81,0.93] LSB1, and the integral nonlinearity (INL) is between [-2.33,2.19] LSB1. At the falling edge, the resolution (LSB0) is 11.90 ps, between [-0.73,0.98] LSB0 and [-2.46,1.83] LSB0 for DNL and INL, respectively. In addition, the accuracy reaches 15.25 ps after multiple measurements for different time intervals separately.

An RGB Color Image Steganography Scheme by Binary Lower Triangular Matrix

Steganography is an area where researchers focus on how to develop novel hiding techniques that are aided by the mathematical or computational model. In order to conceal the secret bits in a cover image, the imperceptible property and embedding payload capacity must be maintained. In most of the developed methods, some selective least significant bits (LSBs) of each pixel of the cover image is modified to hide the data which may lead to substantial distortion in the stego-image especially when the payload size is large. Therefore, to attain the trade-off between payload capacity and image quality, the authors have devised a binary lower triangular matrix-based secret message embedding process in which data can be hidden in the color pixel. In this secret message embedding process, the secret data is embedded aided by the binary lower triangular matrix. The formulated mathematical model for the secret message embedding process has ensured a secure embedding technique with reduced aberration on the stego-image. The proposed steganography scheme is preserving significant visual quality while emphasizing the security aspect by adopting an indirect data-hiding mechanism in contrast to the conventional mechanism. Furthermore, for the betterment of the visual properties of the stego-image, we have generically extended the formulation and tested it to check the visual quality. The empirical results of the proposed steganography scheme depict outcomes satisfactorily for the RGB color images. Researchers can explore and apply this novel data-hiding scheme in different data communication applications.

Integrating Coordinate Transformation and Random Sampling Into High-Capacity Reversible Data Hiding in Encrypted Polygonal Models

Reversible data hiding in encrypted media involves using algorithms to perform data encryption to improve the privacy of the original media and hide data for covert communication or access control. This study explores the feasibility of applying coordinate transformation and random sampling to enhance the embedding rate and total embedding capacity of separable reversible data hiding in encrypted polygonal models based on multiple most significant bit (multi-MSB) prediction and Huffman coding. We first transform each vertex coordinate value of the input model into a decimal value between 0 and 1 and then convert the value into numerous binary digits with a user-defined compression threshold. Thereafter, the random sampling concept is used to generate embeddable vertices with only partial neighboring vertices as a reference. Thus, the embedding rate and total embedding capacity can both be increased considerably. The multi-MSB prediction technique is adopted to obtain the embedding capacity of each embeddable vertex, each vertex coordinate value in the proposed study can have a respective embedding length. Finally, the auxiliary information compressed through Huffman coding and an encrypted secret message are embedded in the multi-MSB of each embeddable vertex coordinate value through bit substitution. The experimental results of this study indicate the feasibility of the proposed algorithm.

Path-Based Delay Variation Models for Parallel-Prefix Adders

State-of-the-art static timing analysis algorithms can evaluate worst-case delay in statistical terms. In this paper, a modeling framework is introduced for the evaluation of the maximum-delay Cumulative Density Function (CDF) of an ensemble of parallel-prefix adder topologies. For moderate variations and close-to-nominal supply voltages, the maximum delay of parallel-prefix adders is practically determined by the maximum of a set of near-critical-delay paths around the nominal maximum-delay path. These paths end to the most significant and neighboring bit positions. Matrix-based path delay formulations are derived for the particular set of paths. The introduced matrix formulations are exploited to assess the maximum-delay CDF by means of a multivariate Gaussian CDF. To validate the accuracy of the introduced models, a quantitative comparison of the proposed probabilistic delay models against Spice-level Monte-Carlo simulations is offered for certain parallel-prefix adders. Threshold-voltage variations summarize several process-dependent variation-inducing mechanisms and are modeled as Gaussian variations, introduced to BSIM-4 transistor models for a 16-nm technology node. For the nominal voltage case and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$10\%$</tex-math></inline-formula> threshold-voltage variations, the introduced models estimate the 0.95 timing yield point with a mean absolute error below <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$1\%$</tex-math></inline-formula> compared to Spice-level simulations for the 16 bit-length case. Furthermore, an extension of the proposed approach to account for multiple end points is investigated that reduces the error for the estimation of maximum delay, demonstrated for a unit delay model and certain bit-lengths of Kogge-Stone adder.

APPLICATION OF A MATHEMATICAL MODEL FOR THE GENERATION OF SEPARATE ELEMENTS OF A STEGANOGRAPHIC SYSTEM IN A HIGHER EDUCATION INSTITUTION

The article presents the method of generating separate elements of the steganographic system based on the combination of cryptography and steganography methods, which makes it possible to increase the level of information protection and develop more effective new non-traditional methods of ensuring information security in the global network. Considering the constant development and improvement of computer cryptography and steganography methods, the study of this particular area of steganoanalysis is the most relevant. &#x0D; It is proposed to apply the method of replacing the least significant bits (LSB method), because it, in combination with the RSA cryptographic algorithm, allows to ensure a high level of information security and the speed of embedding and extraction of a large amount of information.&#x0D; The practical value lies in the ability to quickly generate steganographic containers and ensure reliable encryption and decryption of hidden information in them. At the stage of experimental research, the proposed method of replacing the younger bits was compared with other methods that could be used to generate individual elements of the steganographic system. According to research results, the LSB method has clearly confirmed its effectiveness. The results of the experiment showed the high stability and quality of the received data encryption and decryption method when sending it through an open communication channel (e-mail).

A New ECG Steganography Based on Enhanced Coefficient Adjustment Technique and Least Significant Bit Substitution

A New ECG Steganography Based on Enhanced Coefficient Adjustment Technique and Least Significant Bit Substitution

Digital image watermarking using discrete cosine transformation based linear modulation

The proportion of multimedia traffic in data networks has grown substantially as a result of advancements in IT. As a result, it's become necessary to address the following challenges in protecting multimedia data: prevention of unauthorized disclosure of sensitive data, in addition to tracking down the leak's origin, making sure no alterations may be made without permission, and safeguarding intellectual property for digital assets. watermarking is a technique developed to combat this issue, which transfer secure data over the network. The main goal of invisible watermarking is a hidden exchange of data and a message from being discovered by a third party. The objective of this work is to develop a digital image watermarking using discrete cosine transformation based linear modulation. This paper proposed an invisible watermarking method for embedding information into the transformation domain for the grey scale images. This method used the embedding of a stego-text into the least significant bit (LSB) of the Discrete Cosine Transformation (DCT) coefficient by using a linear modulation algorithm. Also, a stego-text is embedded with different sizes ten times within images after embedding the stego-image immune to different kinds of attack, such as salt and pepper, rotation, cropping, and JPEG compression with different criteria. The proposed method is tested using four benchmark images. Also, to evaluate the embedding effect, PSNR, NC and BER are calculated. The outcomes show that the proposed approach is practical and robust, where the obtained results are promising and do not raise any suspicion. In addition, it has a large capacity, and its results are imperceptible, especially when 1bit/block is embedded.

CPFloat: A C Library for Simulating Low-precision Arithmetic

One can simulate low-precision floating-point arithmetic via software by executing each arithmetic operation in hardware and then rounding the result to the desired number of significant bits. For IEEE-compliant formats, rounding requires only standard mathematical library functions, but handling subnormals, underflow, and overflow demands special attention, and numerical errors can cause mathematically correct formulae to behave incorrectly in finite arithmetic. Moreover, the ensuing implementations are not necessarily efficient, as the library functions these techniques build upon are typically designed to handle a broad range of cases and may not be optimized for the specific needs of rounding algorithms. CPFloat is a C library for simulating low-precision arithmetics. It offers efficient routines for rounding, performing mathematical computations, and querying properties of the simulated low-precision format. The software exploits the bit-level floating-point representation of the format in which the numbers are stored and replaces costly library calls with low-level bit manipulations and integer arithmetic. In numerical experiments, the new techniques bring a considerable speedup (typically one order of magnitude or more) over existing alternatives in C, C++, and MATLAB. To our knowledge, CPFloat is currently the most efficient and complete library for experimenting with custom low-precision floating-point arithmetic.