A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces

Abstract

This article presents a 25-Gb/s single-ended four-level pulse-amplitude modulation (PAM-4) receiver with a time-windowed least significant bit (LSB) decoder for high-speed memory interfaces. The proposed PAM-4 decoding technique obviates the need for additional comparators and reference voltages that are required in conventional PAM-4 decoders. Similar to conventional non-return-to-zero (NRZ) receivers, the proposed PAM-4 receiver uses only one comparator by decoding the LSB through time-windowing the outputs of the comparator that is used to decide a most significant bit (MSB). Therefore, the additional power overhead from a power-hungry analog front-end (AFE) and high-speed clock buffers is minimized in the proposed PAM-4 receiver because it is proportional to the number of comparators. Accordingly, the proposed PAM-4 receiver can achieve superior energy efficiency. Furthermore, the elimination of the use of reference voltages reduces the hardware cost and design complexity. A prototype single-ended PAM-4 receiver was fabricated in a 28-nm CMOS technology. It occupies 0.008 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> and consumes 0.34 pJ/bit at 25 Gb/s.