Polysilicon TFT Research Articles

P‐97: Applying a generative model to improve TFT measurement capacity performance

AMOLED is based on current driving, so the current characteristics of TFT IV(current per voltage) have much influence. Now, as the technology of AMOLED is expanded to HOP(hybrid of Oxide and Polysilicon TFT) and UPC(Under Panel Camera), polysilicon and oxide TFT are used in combination, and TFTs of various sizes must be used at the same time. So, first, it is attempted to reduce the IV measurement points and improve them with the known interpolation method. However, there is a limit to accurate prediction due to the non‐linear characteristics of TFT and noise measurement in the off region of TFT.In this paper, we applied an asymmetric neural network structure to overcome this limitation of reduction decoding. To do this, we developed an asymmetric autoencoder to decode or reconstruct TFT IV data from small sampled IV measurements (14~35%). Then, to overcome the error estimation of generating many errors in the surrounding interpolation because noise is included in the TFT off region, a function of partially removing noise only in the off region is introduced. In addition, to overcome the performance decrease problem due to the minimal amount of abnormal data, which should be accurately predicted in a situation close to abnormal, generative models were applied to overcome it. The IV information to be generated was encoded using a pretrained large language model to reduce the dimensionality and converted into text, which was then trained on the distillate GPT‐2 model and used as a generative model. In the general interpolation method, the performance decreases as the number of measurement samples are reduced; the method proposed in this paper maintains its performance even if the sampling is under 20%. This means that it is adequate to restore only a small portion of information using the latent space information that has learned the TFT IV saturation and linear mode characteristics. This is applied to mass production by increasing the measurement capability without additional equipment investment.

40‐3: Distinguished Paper: Reliable low‐power high‐performance low‐temperature polycrystalline thin‐film transistor technologies in bottom gate‐controlled device architectures for AMOLED displays

This paper presents recent process for bottom gate‐controlled low‐temperature polysilicon (LTPS) TFT technologies for reliable low‐power high‐performance AMOLED displays. Experimental and physics‐based analysis leads to the pragmatic device design concept for LTPS TFT performance enhancement. Process integration of bottom (second) gate and top (first) gate metals, controlled by optimal two gates‐based device structures, is explored in conjunction of improved poly crystallization and poly‐Si/gate‐oxide interface by reducing defect density‐of‐state (DOS), especially in the grain boundaries of the channel region. We obtain optimal device performance such as optimal sub‐threshold slope, high driver current (Ion), and low leakage current (Ioff), in addition to enhanced device reliability characteristics. Numerical device simulations, supplemented by physics‐based analysis, are performed to corroborate experimental results in fabricated TFTs, as well as gain more physical insight in the bottom‐gate LTPS device configuration, to enable reliable low‐power high‐performance AMOLED display applications.

Reliable low‐power high‐performance low‐temperature polycrystalline thin‐film transistor technologies in bottom gate‐controlled device architectures for AMOLED displays

AbstractThis paper presents a recent process for bottom gate‐controlled low‐temperature polysilicon (LTPS) TFT technologies for reliable low‐power high‐performance AMOLED displays. The experimental and physics‐based analysis leads to the pragmatic device design concept for LTPS TFT performance enhancement. The process integration of bottom (second) gate and top (first) gate metals, controlled by optimal two gates‐based device structures, is explored in conjunction with improved poly crystallization and poly‐Si/gate‐oxide interface by reducing defect density‐of‐state (DOS), especially in the grain boundaries of the channel region. We obtain optimal device performance, such as optimal sub‐threshold slope, high driver current (Ion), and low leakage current (Ioff), in addition to enhanced device reliability characteristics. Numerical device simulations, supplemented by physics‐based analysis, are performed to corroborate experimental results in fabricated TFTs and gain more physical insight into the bottom‐gate LTPS device configuration to enable reliable low‐power high‐performance AMOLED display applications.

P‐117: AI Analysis of HOP Circuit Failure and Improvement

AMOLED's HOP(hybrid of Oxide semiconductor and Polysilicon TFT) technology was born to meet the market's demand for low power consumption. Also, the IGZO oxide process was introduced with new driving technology to support the low driving frequency operation. However, this new GC circuit of oxide TFT driving caused new and randomly appearing horizontal defects which do not exist in LTPS circuits. To solve this issue, we studied to find the design parameters using pipelined deep learning models composed of CGAN(Conditional Generative Adversarial Network), VGM(Variational Gaussian Mixture), and XAI(eXplainable Artificial intelligence) technologies to figure out what causes these defects. We collected HOP panel design information to achieve the given goal and confirmed the degree of defect per HOP model. Since the number of HOP models is limited, XAI analysis might also be negligible. We solve this issue by generating data using CGAN and VGM in sequence. After, ALE(Accumulated Local Effects), a popular XAI technique, is applied to find affected design parameters and change‐related circuit designs to help verify the proposed algorithm's performance. As a result of this design change, we identified that the related defect rate decreases from 15000ppm to less than 500 ppm, in which XAI plays a significant role in solving a newly introduced defect issue. That was believed for a long time a challenging problem to analyze using the legacy SPICE tool in the OLED circuit field. Our result also suggests that even predicting the defect rate of future HOP models becomes feasible with our proposed deep learning architecture.

14‐3: Extremely Short‐Channel LTPS TFT Technologies for High‐Performance Low‐Power, and Reliable AMOLED displays

This paper presents recent progress to scale down low‐temperature polysilicon (LTPS) TFT technologies in the extremely short‐channel length regime for AMOLED displays. Process integration of short‐channel gate and narrow‐width polysilicon into scaled equivalent gate‐oxide thickness (EOT), is explored, in conjunction with enhanced poly crystallization by reducing defect density‐of‐state (DOS) especially in the grain boundaries of the channel region. We obtain more than twice higher current drive (Ion) with significantly‐reduced parasitic gate capacitance, thereby enabling high‐performance high‐frequency panel operations. In addition to superior panel performance in scaled LTPS TFTs, reliable devices are attained, demonstrating robust device characteristics for negative‐bias instability (NBTI) and hot carrier injection (HCI) effects. Physics‐based analysis, based on experimental data and numerical device simulations, is performed to gain more insight in the TFT technologies.

36‐2: Invited Paper: LCD with Integrated In‐cell Fingerprint Sensor

This paper presents a novel optical type in‐cell fingerprint sensor (iFP) technology, which can detect a user's fingerprint on display. By using low temperature polysilicon (LTPS) TFT process, new sensor material, and active pixel sensor circuit (APS), this sensor can detect a fingerprint image with good performance. The FPS/Touch/Display Driver IC (FTDI) is also implemented in this work, and successfully demonstrated.

Enhancing Hot-Carrier Reliability of Dual-Gate Low-Temperature Polysilicon TFTs by Increasing Lightly Doped Drain Length

In this article, an n-type double-gate low-temperature polysilicon (LTPS) TFT is investigated. Previous work has confirmed that the hot-carrier effect will cause impact ionization. Here we observed that, after hot-carrier stress (HCS), the transfer curve in the saturation region has a negative Vth shift, and a hump is also observed. The reverse output characteristic shows that gate induced drain leakage (GIDL) of the transistor gradually increases and the subthreshold swing (S.S.) has a tendency to collapse. In structures with longer lightly doped drain (LDD) lengths, the electric field at both source/drain side can be effectively dispersed. Thereby, an extended LDD can reduce the overall degradation, and a physical model of explanation is proposed. By using the energy band diagram, we clarify how the additional electron hole pairs affect the output property. Next, Silvaco TCAD simulation is utilized to illustrate the electric field distribution and validate the physical model.

Impact of the Inhomogenous Structure of Polysilicon TFT's Active Layer on the Electrostatic Potential Distribution

Recently polycrystalline silicon (pc-Si) thin film transistors (TFT’s) have emerged as the devices of choice for many applications. The TFTs made of a thin un-doped polycrystalline silicon film deposited on a glass substrate by the Low Pressure Chemical Vapor Deposition technique LPCVD have limits in the technological process to the temperature < 600°C. The benefit of pc-Si is to make devices with large grain size. Unfortunately, according to the conditions during deposition, the pc-Si layers can consist of a random superposition of grains of different sizes, where grains boundaries parallels and perpendiculars appear. In this paper, the transfer characteristics IDS-VGS are simulated by solving a set of two-dimensional (2D) drift-diffusion equations together with the usual density of states (DOS: exponential band tails and Gaussian distribution of dangling bonds) localized at the grains boundaries. The impact of thickness of the active layer on the distribution of the electrostatic potential and the effect of density of intergranular traps states on the TFT’s transfer characteristics IDS-VGS have been also investigated.

Impact of film thickness on threshold voltage of polysilicon TFTs

The threshold voltage is a key parameter in the silicon MOSFETS design and operation. In this paper, we study the factors that contribute to the changes of threshold voltage of thin-film LPCVD polysilicon transistors when varying the thickness of the active layer. The results show that the threshold voltage depends strongly on the film thickness. For high thicknesses, the threshold voltage is shown to be determined by the trapped holes at grain boundaries. The variation of this parameter with film thickness can be attributed to inter-granular trap states density variation in the film. For low thicknesses, a simple electrostatic model of the study structure, associated with a numerical method of solving 2D-Poisson's equations, shows that the changes of threshold voltage of polysilicon TFT depends on grain-boundary properties and charge-coupling between the front and back gates. Based on this consideration, the usual threshold voltage expression is modified. The results so obtained are compared with the available experimental data, which show a satisfactory match thus justifying the validity of the proposed relation.

MILC PMOS Poly-Silicon TFT Circuits and Application in SOP

Research towards thin film circuits is one of the most attractive directions of the large-area electronics and flexible electronics. In this work, the research on TFT shift register circuit which is critical for system integration on panel (SOP) is presented. The whole circuit is composed of MILC PMOS poly-Si TFTs. The TFT device exhibited field-effect mobility of 65.21cm2/Vs, threshold voltage of -3.5V and sub-threshold swing of 0.56V/dec. Some special design considerations were adopted to improve the robustness of the circuits. The whole shift register is composed of as many as 180 stages and exhibited well performance with frame frequency from 22Hz to 220Hz at the power supply voltage of 11V. No signal attenuation and distortion appeared from the first to the final stage. The effect of bootstrapping and dynamic behavior is analyzed. The fabrication and reliability analysis are also discussed in this paper. Overall, the high performance driver circuits based on our MILC PMOS process are possible and have the potential in the application of SOP.

Impact of Negative-Bias-Temperature-Instability on Channel Bulk of Polysilicon TFT by Gated PIN Diode Analysis

Impact of Negative-Bias-Temperature-Instability on Channel Bulk of Polysilicon TFT by Gated PIN Diode Analysis

47.2: 2.8‐inch WQVGA Flexible AMOLED Using High Performance Low Temperature Polysilicon TFT on Plastic Substrates

AbstractThis paper reports a low‐temperature polycrystalline silicon (LTPS) fabrication process on plastic substrate for a flexible AMOLED display. Characteristics of fabricated TFTs showed excellent performance with field effect mobility of 124.1 cm2/V‐s, on/off ratio of >108, subthreshold slope of 0.30V/dec, and threshold voltage of −2.03V. Internal scan drive circuits, 1:3 demux, and compensation circuits were successfully integrated on the backplane of a 166ppi 2.8″ WQVGA flexible AMOLED panel.

A New Method for High-Speed Dynamic TSPC Memory by Low-Temperature Poly Silicon TFT Technology

We propose an 8 by 8 dynamic true-single-phase-clock (TSPC) circuit based on low-temperature polycrystalline silicon (LTPS) technology to perform high speed dynamic memory cell. The proposed method allows the memory access rate to reach 25 MHz, in contrast to the traditional LTPS memory, with static circuit design, that operates at a low frequency of only about 6 MHZ. The 8 by 8 dynamic TSPC LTPS memory cell can be applied in high speed circuits. The experimental results show that the proposed 8 by 8 dynamic TSPC LTPS memory cell, operating at 25 MHz, can achieve high speed effectively. We believe it will be the most suitable technology to realize high speed memory for system on a panel (SOP) together with IC chip technology.

Temperature Coefficient of Poly-Silicon TFT and its Application on Voltage Reference Circuit With Temperature Compensation in LTPS Process

The temperature coefficient (TC) of n-type polycrystalline silicon thin-film transistors (poly-Si TFTs) is investigated in this paper. The relationship between the TC and the activation energy is observed and explained. From the experimental results, it is also found that TC is not sensitive to the deviation of the laser crystallization energy. On the contrary, channel width can effectively modulate the TC of TFTs. By using the diode-connected poly-Si TFTs with different channel widths, the first voltage reference circuit with temperature compensation for precise analog circuit design on glass substrate is proposed and realized. From the experimental results in a low-temperature poly-Si process, the output voltage of voltage reference circuit with temperature compensation exhibits a very low TC of 195 ppm/degC , between 25degC and 125degC. The proposed voltage reference circuit with temperature compensation can be applied to design precise analog circuits for system-on-panel or system-on-glass applications, which enables the analog circuits to be integrated in the active-matrix liquid crystal display panels.

P‐56: One‐Chip Driver IC for 16 Million Color WXGA LTPS TFT LCD Panel

AbstractOne‐chip driver IC for 16 million color (24‐bit color depth) wide extended graphic array (WXGA) low‐temperature polysilicon (LTPS) TFT LCD panel is presented. It adopts the 1:6 demuxing scheme to integrate multiple source driver ICs on a single chip. Also, it incorporates a timing controller (T/CON), a LVDS receiver and level shifters to generate control signals to the panel.

P‐259L: Late‐News Poster: A 14inch Uniform AMOLED Display with Low Cost PECVD Based Microcrystalline Silicon TFT Backplanes

AbstractThis paper discusses development of uniform 14.1 inch AMOLED display using PECVD based microcrystalline silicon (mc‐Si) TFTs. Microcrystalline silicon was deposited using conventional 13.56 MHz Plasma Enhanced Chemical Vapor Deposition (PECVD) with novel gas precursors. The mc‐Si TFT's show a field effect mobility of around 1cm2/V.s and off‐current less than 1pA. Electrical stress on mc‐Si TFTs for a long time shows no significant threshold voltage shift indicating a stable TFT backplane. Significant uniformity improvements were made with novel TFT structure to give uniform AMOLED display. The deposition time for mc‐Si TFTs was significantly reduced by using a thin mc‐Si layer. Mc‐Si TFT backplanes using conventional PECVD equipment offers significant cost advantages over other competing laser and non‐laser polysilicon TFT technologies for AMOLEDs.

A novel SLS ELA crystallization process and its effects on polysilicon film defectivity and TFT performance

Polysilicon TFTs fabricated in films crystallized with a novel SLS ELA technique were investigated. The TFT channels were oriented along the preferential direction and vertical to it, probing both directions’ grain quality. DLTS assessment was conducted on unstressed TFTs in order to probe the film’s defect nature. DC hot-carrier stress was applied for both channel orientations, in order to elucidate the effect of the crystallization procedure on TFT reliability. A dimensional optimization of the TFTs was found.

UHF RFCPUs on Flexible and Glass Substrates for Secure RFID Systems

A radio frequency integrated circuit (RFIC) tag consisting of an 8 bit CPU, a 4 kB ROM, a 512B SRAM, and an RF circuit, which communicates using 915 MHz UHF RF signals, has been developed on both a flexible substrate and a glass substrate. Each of the RFIC tags employs a single DES and an anti-side channel attack routine in firmware for secured communication, and occupies an area of 10.5 mm in width and 8.9 mm in height. The RFIC tag on the flexible substrate is 145 mum thick and weighs 262 mg, and the RFIC tag on the glass substrate consumes 0.54 mW at a power supply voltage of 1.5 V and communicates with a maximum range of 43 cm at a power of 30 dBm. The high-performance poly-silicon TFT technology on flexible substrate and glass substrate of 0.8 mum design rule, and a gate plus one metal layer are used for fabrication. The RFIC tag realizes stable internal clock generation and distribution by a digital control clock generator and a two-phase nonoverlap clock scheme, respectively.

13.1: Invited Paper: Technological Evolution for Large Screen Size Active Matrix OLED Display

AbstractVacuum evaporation process with metal mask using LTPS (Low Temperature Poly Silicon TFT) backplane is well established OLED production process. However this technology is not applicable for large sized display like TV. Various technologies to break through this constraint have been proposed so far. In this paper pros and cons of these proposed technologies are discussed and new approach, micro silicon TFT with unique anneal technology and laser transfer OLED process, is presented.

230 DPI High Resolution AMPLED Display on Flexible Metal Foils with Integrated Row Drivers

This paper presents a 230 dpi Active Matrix Polymer Light Emitting Diode (AMPLED) display on flexible stainless steel substrates fabricated with laser annealed poly-silicon TFT technology. The high resolution display is based on the standard 2 TFT pixel circuitry to form a full VGA array. Polysilicon TFT based shift registers for integrated row driving are also demonstrated. Display fabrication is compatible with standard polysilicon TFT CMOS processing temperatures and conditions. This paper discusses backplane fabrication, PLED deposition and display encapsulation; all performed in-house.