Impact of film thickness on threshold voltage of polysilicon TFTs

Abstract

The threshold voltage is a key parameter in the silicon MOSFETS design and operation. In this paper, we study the factors that contribute to the changes of threshold voltage of thin-film LPCVD polysilicon transistors when varying the thickness of the active layer. The results show that the threshold voltage depends strongly on the film thickness. For high thicknesses, the threshold voltage is shown to be determined by the trapped holes at grain boundaries. The variation of this parameter with film thickness can be attributed to inter-granular trap states density variation in the film. For low thicknesses, a simple electrostatic model of the study structure, associated with a numerical method of solving 2D-Poisson's equations, shows that the changes of threshold voltage of polysilicon TFT depends on grain-boundary properties and charge-coupling between the front and back gates. Based on this consideration, the usual threshold voltage expression is modified. The results so obtained are compared with the available experimental data, which show a satisfactory match thus justifying the validity of the proposed relation.